Intel AUGSBURG S775 I915G MATX 10PK KD915GAGLKPAK10 ユーザーズマニュアル

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Error Messages and Beep Codes 
Table 52.  Runtime Code Uncompressed in F000 Shadow RAM (continued) 
Code 
Description of POST Operation 
AE 
Uncompress SMBIOS module and init SMBIOS code and form the runtime SMBIOS image in 
shadow. 
B1 
Going to copy any code to specific area. 
00 
Copying of code to specific area done.  Going to give control to INT-19 boot loader. 
4.3  Bus Initialization Checkpoints 
The system BIOS gives control to the different buses at several checkpoints to do various tasks. 
Table 53 describes the bus initialization checkpoints. 
Table 53.  Bus Initialization Checkpoints 
Checkpoint Description 
2A 
Different buses init (system, static, and output devices) to start if present. 
38 
Different buses init (input, IPL, and general devices) to start if present. 
39 
Display different buses initialization error messages. 
95 
Init of different buses optional ROMs from C800 to start. 
 
While control is inside the different bus routines, additional checkpoints are output to port 80h as 
WORD to identify the routines under execution.  In these WORD checkpoints, the low byte of the 
checkpoint is the system BIOS checkpoint from which the control is passed to the different bus 
routines.  The high byte of the checkpoint is the indication of which routine is being executed in the 
different buses.  Table 54 describes the upper nibble of the high byte and indicates the function that 
is being executed. 
Table 54.  Upper Nibble High Byte Functions 
Value Description 
func#0, disable all devices on the bus concerned. 
func#1, static devices init on the bus concerned. 
func#2, output device init on the bus concerned. 
func#3, input device init on the bus concerned. 
func#4, IPL device init on the bus concerned. 
func#5, general device init on the bus concerned. 
func#6, error reporting for the bus concerned. 
func#7, add-on ROM init for all buses. 
 
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