Intel Xeon® Processor X3430 (8M Cache, 2.40 GHz) BX80605X3430 ユーザーズマニュアル

製品コード
BX80605X3430
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Processor Integrated I/O (IIO) Configuration Registers
178
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
3.7.2.3
CAPHDRH—PCI Express Capability Header High Register
Capability header (capability ID) for this extended function.
§
11:8
RW
0
VC1 Maximum 
Maximum tags that can be used for VC1 (Azalia) Traffic. Value should not be 
set greater then MaxRequests. It is required that “Pool Index” in 
QPI[0]PORB— QPI[0] Protocol Outgoing Request Buffer be disabled when Isoc 
traffic is enabled. 
When Isoc is enabled this value must be set to >0.
0–7 = Maximum TIDs pending on Intel QuickPath Interconnect with critical 
priority set.
>7 = Reserved
Recommend setting (VC1 max) = 4
7:4
RW
0
VCp Reserved 
Number of TIDs that are reserved for VCp (legacy Isoc) Traffic. The value must 
be less then “MaxRequest minus the Reserved for Critical priority”. Should be 
set no greater than the “VCp Maximum” value.
0–7 = legal values
>7 = reserved
Recommend setting (VCp) = 2
3:0
RW
0
VCp Maximum 
Maximum tags that can be used for VCp (legacy Isoc) Traffic. Value should not 
be set greater then MaxRequests. It is required that “Pool Index” in 
QPI[0]PORB—QPI[0] Protocol Outgoing Request Buffer be disabled when Isoc 
traffic is enabled. When Isoc is enabled this value must be set to >0.
0–7 = Maximum TIDs pending on Intel QuickPath Interconnect with critical 
priority set.
>7 = Reserved
Recommend setting (VCp max) = 4
Register:
 QPIPISOCRES
Device:
 16
Function:  1
Offset:
 B8h
Bit
Attr
Default
Description
Device: 16
Function: 1
Offset: 100h
Bit
Attr
Default
Description
31:0
RO
000Bh
CAPIDH
000Bh is the Capability ID for vendor specific