Motorola DSP56012 ユーザーズマニュアル
5-16
DSP56012 User’s Manual
MOTOROLA
Serial Host Interface
Serial Host Interface Programming Model
suspended before transmitting an ACK. While HIDLE is cleared the bus is busy, that
is, the start event was sent but no Stop event was generated. Setting HIDLE will
cause a stop event.
is, the start event was sent but no Stop event was generated. Setting HIDLE will
cause a stop event.
Note:
HIDLE is set while the SHI is not in the I
2
C Master mode. HIDLE is set during
hardware reset, software reset, individual reset, and while the chip is in the
Stop state.
Stop state.
5.4.6.9
HCSR Bus-Error Interrupt Enable (HBIE)—Bit 10
The read/write HCSR Bus-error Interrupt Enable (HBIE) control bit is used to enable
the SHI bus-error interrupt. If HBIE is cleared, bus-error interrupts are disabled, and
the HBER status bit must be polled to determine if an SHI bus error occurred. If both
HBIE and HBER are set, the SHI will request SHI bus-error interrupt service from the
interrupt controller. HBIE is cleared by hardware reset and software reset.
the SHI bus-error interrupt. If HBIE is cleared, bus-error interrupts are disabled, and
the HBER status bit must be polled to determine if an SHI bus error occurred. If both
HBIE and HBER are set, the SHI will request SHI bus-error interrupt service from the
interrupt controller. HBIE is cleared by hardware reset and software reset.
Note:
Clearing HBIE will mask a pending bus-error interrupt only after a
one-instruction-cycle delay. If HBIE is cleared in a long interrupt service
routine, it is recommended that at least one other instruction separate the
instruction that clears HBIE and the RTI instruction at the end of the interrupt
service routine.
one-instruction-cycle delay. If HBIE is cleared in a long interrupt service
routine, it is recommended that at least one other instruction separate the
instruction that clears HBIE and the RTI instruction at the end of the interrupt
service routine.
5.4.6.10
HCSR Transmit-Interrupt Enable (HTIE)—Bit 11
The read/write HCSR Transmit-Interrupt Enable (HTIE)
control bit is used to enable
the SHI transmit data interrupts. If HTIE is cleared, transmit interrupts are disabled,
and the HTDE status bit must be polled to determine if the SHI transmit-data register
is empty. If both HTIE and HTDE are set and HTUE is cleared, the SHI will request
SHI transmit-data interrupt service from the interrupt controller. If both HTIE and
HTUE are set, the SHI will request SHI transmit-underrun-error interrupt service
from the interrupt controller. HTIE is cleared by hardware reset and software reset.
and the HTDE status bit must be polled to determine if the SHI transmit-data register
is empty. If both HTIE and HTDE are set and HTUE is cleared, the SHI will request
SHI transmit-data interrupt service from the interrupt controller. If both HTIE and
HTUE are set, the SHI will request SHI transmit-underrun-error interrupt service
from the interrupt controller. HTIE is cleared by hardware reset and software reset.
Note:
Clearing HTIE will mask a pending transmit interrupt only after a
one-instruction cycle-delay. If HTIE is cleared in a long interrupt service
routine, it is recommended that at least one other instruction separate the
instruction that clears HTIE and the RTI instruction at the end of the interrupt
service routine.
one-instruction cycle-delay. If HTIE is cleared in a long interrupt service
routine, it is recommended that at least one other instruction separate the
instruction that clears HTIE and the RTI instruction at the end of the interrupt
service routine.
5.4.6.11
HCSR Receive Interrupt Enable (HRIE[1:0])—Bits 13–12
The read/write HCSR Receive Interrupt Enable (HRIE[1:0])
control bits are used to
enable the SHI receive-data interrupts. If HRIE[1:0] are cleared, receive interrupts are
disabled, and the HRNE and HRFF (bits 17 and 19, see below) status bits must be
polled to determine if there is data in the receive FIFO. If HRIE[1:0] are not cleared,
receive interrupts will be generated according to
disabled, and the HRNE and HRFF (bits 17 and 19, see below) status bits must be
polled to determine if there is data in the receive FIFO. If HRIE[1:0] are not cleared,
receive interrupts will be generated according to