Motorola DSP56012 ユーザーズマニュアル
8-10
DSP56012 User’s Manual
MOTOROLA
Digital Audio Transmitter
DAX Internal Architecture
8.5.4.10
DAX Channel B User Data (XUB)—Bit 14
The value of the XUB bit is transmitted as the thirtieth bit (Bit 29) of the Channel B
sub-frame in the next frame.
sub-frame in the next frame.
Note:
This bit is not affected by any of the DAX reset states.
8.5.4.11
DAX Channel B Channel Status (XCB)—Bit 15
The value of the XCB bit is transmitted as the thirty-first bit (Bit 30) of the Channel B
sub-frame in the next frame.
sub-frame in the next frame.
Note:
This bit is not affected by any of the DAX reset states.
8.5.5
DAX Status Register (XSTR)
The XSTR is a 24-bit read-only register that contains the DAX status flags. The
contents of the XSTR are shown in
contents of the XSTR are shown in
described in the following paragraphs.
8.5.5.1
DAX Audio Data Register Empty (XADE)—Bit 0
When cleared, the XADE status flag indicates that the DAX audio data registers are
empty (and ready to receive the next audio data). This bit is set at the beginning of
every frame transmission (more precisely, when an audio data upload from the
XADRA/XADRB to XADSR/XADBUF occurs). When XADE is set and the DAX
interrupt is enabled (XIEN = 1), a DAX interrupt request with the Transmit Data
Empty interrupt vector is sent to the DSP core.
empty (and ready to receive the next audio data). This bit is set at the beginning of
every frame transmission (more precisely, when an audio data upload from the
XADRA/XADRB to XADSR/XADBUF occurs). When XADE is set and the DAX
interrupt is enabled (XIEN = 1), a DAX interrupt request with the Transmit Data
Empty interrupt vector is sent to the DSP core.
Note:
XADE is cleared by writing data to XADRA and XADRB. It is cleared by
software reset and hardware reset, and by the Stop state.
software reset and hardware reset, and by the Stop state.
8.5.5.2
XSTR Reserved Bits—Bits 1, 5–23
These XSTR bits are reserved and unused. They read as 0s, and should be written
with 0s to ensure compatibility with future device versions.
with 0s to ensure compatibility with future device versions.
8.5.5.3
DAX Transmit Underrun Error Flag (XAUR)—Bit 2
The XAUR status flag is set when the DAX audio data registers (XADRA/XADRB)
are empty (XADE = 1) and the next audio data upload occurs. When a DAX
underrun error occurs, the previous data will be re-transmitted. This bit alone does
not cause any interrupts. However, it causes a change in the interrupt vector that is
sent to DSP core, if an interrupt is generated. This allows programmers to write an
exception handling routine for this special case.
are empty (XADE = 1) and the next audio data upload occurs. When a DAX
underrun error occurs, the previous data will be re-transmitted. This bit alone does
not cause any interrupts. However, it causes a change in the interrupt vector that is
sent to DSP core, if an interrupt is generated. This allows programmers to write an
exception handling routine for this special case.