Renesas R5S72641 ユーザーズマニュアル
Section 10 Direct Memory Access Controller
Page 386 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
31
TC
0
R/W
Transfer Count Mode
Specifies whether to transmit data once or for the
count specified in DMATCR by one transfer request.
This function is valid only in on-chip peripheral module
request mode. Note that when this bit is set to 0, the
TB bit must not be set to 1 (burst mode). Do not set TC
to 1 when a module other than multi-function timer
pulse unit 2, compare-match timer, controller area
network, CD-ROM decoder, or A/D converter is set as
the transfer request source.
count specified in DMATCR by one transfer request.
This function is valid only in on-chip peripheral module
request mode. Note that when this bit is set to 0, the
TB bit must not be set to 1 (burst mode). Do not set TC
to 1 when a module other than multi-function timer
pulse unit 2, compare-match timer, controller area
network, CD-ROM decoder, or A/D converter is set as
the transfer request source.
0: Transmits data once by one transfer request
1: Transmits data for the count specified in DMATCR
by one transfer request
30
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
always be 0.
29
RLDSAR
0
R/W
SAR Reload Function ON/OFF
Enables (ON) or disables (OFF) the function to reload
SAR and DMATCR.
SAR and DMATCR.
0: Disables (OFF) the function to reload SAR and
DMATCR
1: Enables (ON) the function to reload SAR and
DMATCR
28
RLDDAR
0
R/W
DAR Reload Function ON/OFF
Enables (ON) or disables (OFF) the function to reload
DAR and DMATCR.
DAR and DMATCR.
0: Disables (OFF) the function to reload DAR and
DMATCR
1: Enables (ON) the function to reload DAR and
DMATCR
27
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
always be 0.