Renesas R5S72641 ユーザーズマニュアル
Section 11 Multi-Function Timer Pulse Unit 2
R01UH0134EJ0400 Rev. 4.00
Page 487 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
1 OE4A 0 R/W
Master
Enable
TIOC4A
This bit enables/disables the TIOC4A pin output for this
module.
module.
0: Output for this module is disabled (inactive level)*
1: Output for this module is enabled
0 OE3B 0 R/W
Master
Enable
TIOC3B
This bit enables/disables the TIOC3B pin output for this
module.
module.
0: Output for this module is disabled (inactive level)*
1: Output for this module is enabled
Note: * The inactive level is determined by the settings in timer output control registers 1 and 2
(TOCR1 and TOCR2). For details, refer to section 11.3.17, Timer Output Control
Register 1 (TOCR1), and section 11.3.18, Timer Output Control Register 2 (TOCR2).
Set these bits to 1 to enable output for this module in other than complementary PWM
or reset-synchronized PWM mode. When these bits are set to 0, low level is output.
Register 1 (TOCR1), and section 11.3.18, Timer Output Control Register 2 (TOCR2).
Set these bits to 1 to enable output for this module in other than complementary PWM
or reset-synchronized PWM mode. When these bits are set to 0, low level is output.