Renesas R5S72641 ユーザーズマニュアル
Section 18 Serial Sound Interface
R01UH0134EJ0400 Rev. 4.00
Page 905 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
7 to 4
CKDV[3:0] 0000
R/W
Serial Oversampling Clock Division Ratio
Sets the ratio between the oversampling clock (AUDIO
)
and the serial bit clock. When the SCKD bit is 0, the
setting of these bits is ignored. The serial bit clock is used
in the shift register and is supplied from the SSISCK pin.
setting of these bits is ignored. The serial bit clock is used
in the shift register and is supplied from the SSISCK pin.
0000: AUDIO
0001: AUDIO
/2
0010: AUDIO
/4
0011: AUDIO
/8
0100: AUDIO
/16
0101: AUDIO
/32
0110: AUDIO
/64
0111: AUDIO
/128
1000: AUDIO
/6
1001: AUDIO
/12
1010: AUDIO
/24
1011: AUDIO
/48
1100: AUDIO
/96
1101: Setting prohibited
1110: Setting prohibited
1111: Setting prohibited
3 MUEN 0 R/W
Mute
Enable
0: This module is not muted.
1: This module is muted.
Note: When this module is muted, the value of outputting
serial data is re-written to 0 but data transmission is
not stopped. Write dummy data to the SSIFTDR not
to generate a transmit underflow because the
number of data in the transmit FIFO is decreasing.
not stopped. Write dummy data to the SSIFTDR not
to generate a transmit underflow because the
number of data in the transmit FIFO is decreasing.
2
0
R
Reserved
The read value is undefined. The write value should
always be 0.
always be 0.
1 TEN 0 R/W
Transmit
Enable
0: Disables the transmit operation.
1: Enables the transmit operation.