Intel Gigabit Ethernet Controllers ユーザーズマニュアル

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This register reflects the number of receive packets that are currently in the Receive FIFO. This 
register is available for diagnostic purposes only, and should not be written during normal 

operation.

This register stores the head of the Ethernet controller’s on–chip transmit data FIFO. Since the 
internal FIFO is organized in units of 64-bit words, this field contains the 64-bit offset of the 

current Transmit FIFO Head. So a value of “8h” in this register corresponds to an offset of 8 

quadwords into the Transmit FIFO space. This register is available for diagnostic purposes only, 
and should not be written during normal operation.

Reserved

FIFO Tail

FIFO Tail

12:0

0b

A “saved” value of the Receive FIFO Tail pointer.

Reserved

31:13

0b

Reads as 0b. Should be written to 0b for future compatibility.

Reserved

FIFO Tail

RX FIFO

Packet Count

12:0

0b

The number of received packets currently in the RX FIFO.

Reserved

31:13

0b

Reads as 0b. Should be written to 0b for future compatibility.