Intel Gigabit Ethernet Controllers ユーザーズマニュアル

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Driver accessible Wakeup Status registers are excluded from all resets except for 
LAN_PWR_GOOD. This includes:

•

Wakeup Status Register.

•

Wakeup Packet Length.

•

Wakeup Packet Memory.

Finally, the “Wakeup Context” as defined in the PCI Bus Power Management Interface 

Specification is reset on LAN_PWR_GOOD, and is also reset on the deassertion of RST# if 

AUX_POWER = 0b. This includes:

•

PME_En bit of the Power Management Control/Status Register (PMCSR).

•

PME_Status bit of the Power Management Control/Status Register (PMCSR).

The shadow copies of these bits in the Wakeup Control Register are treated identically.

Statistics registers are hardware-initialized to values as detailed in each particular register’s 

description. The initialization of these registers begins upon transition to D0

active 

power state 

(when internal registers become accessible, as enabled by setting the Memory Access Enable of the 
PCI Command register), and is guaranteed to be completed within 1 µs of this transition. Access to 

statistics registers prior to this interval can return indeterminate values. Given typical system boot 

times and the software driver’s Ethernet controller initialization routines, no initialization of these 
registers through software should be necessary.