Freescale Semiconductor MCF52211 ユーザーズマニュアル
EzPort
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
19-6
Freescale Semiconductor
19.4.1.5
Read Data
The Read Data command returns data from the flash memory, starting at the address specified in the
command word. Data continues being returned for as long as the EzPort chip select (EZPCS) is asserted,
with the address automatically incrementing. When the address reaches the highest flash memory address,
it wraps around to the lowest flash memory address. In this way, the entire contents of the flash memory
can be returned by one command.
command word. Data continues being returned for as long as the EzPort chip select (EZPCS) is asserted,
with the address automatically incrementing. When the address reaches the highest flash memory address,
it wraps around to the lowest flash memory address. In this way, the entire contents of the flash memory
can be returned by one command.
For this command to return the correct data, the EzPort Clock (EZPCK) must run at no more than divide
by eight of the internal system clock.
by eight of the internal system clock.
This command should not be used if the write error flag is set, or a write is in progress. This command is
not accepted if flash security is enabled.
not accepted if flash security is enabled.
19.4.1.6
Read Data at High Speed
This command is identical to the Read Data command, except for the inclusion of a dummy byte following
the address bytes and before the first data byte is returned.
the address bytes and before the first data byte is returned.
This allows the command to run at any frequency of the EzPort Clock (EZPCK) up to and including half
the internal system clock frequency of the micro-controller.This command should not be used if the write
error flag is set, or a write is in progress. This command is not accepted if flash security is enabled.
the internal system clock frequency of the micro-controller.This command should not be used if the write
error flag is set, or a write is in progress. This command is not accepted if flash security is enabled.
19.4.1.7
Page Program
The Page Program command programs locations in flash memory that have previously been erased. The
starting address of the memory to program is sent after the command word and must be a 32-bit aligned
address (the two LSBs must be zero). After every four bytes of data are received by the EzPort, that 32-bit
word is programmed into flash memory with the address automatically incrementing after each write. For
this reason, the number of bytes to program must be a multiple of four. Only a maximum of 256 bytes can
be programmed at a time; when the address reaches the highest address within any given 256-byte space
of memory, it wraps around to the lowest address in that same space.
starting address of the memory to program is sent after the command word and must be a 32-bit aligned
address (the two LSBs must be zero). After every four bytes of data are received by the EzPort, that 32-bit
word is programmed into flash memory with the address automatically incrementing after each write. For
this reason, the number of bytes to program must be a multiple of four. Only a maximum of 256 bytes can
be programmed at a time; when the address reaches the highest address within any given 256-byte space
of memory, it wraps around to the lowest address in that same space.
This command should not be used if the write error flag is set, a write is in progress, the write enable bit
is not set, or the configuration register has not been written.This command is not accepted if flash security
is enabled.
is not set, or the configuration register has not been written.This command is not accepted if flash security
is enabled.
The write error flag sets if there is an attempt to program a protected area of the flash memory.
Table 19-4. EzPort Configuration Register Field Description
Field
Descriptions
7
—
Reserved, should be cleared.
6
PRDIV
Enables prescaler divide by 8.
0 The system clock is fed directly into the divider.
1 Enables a prescaler that divides the system clock by 8 before it enters the divider.
0 The system clock is fed directly into the divider.
1 Enables a prescaler that divides the system clock by 8 before it enters the divider.
5–0
DIV[5:0]
Clock divider field. The combination of PRDIV8 and DIV[5:0] effectively divides the system clock down to a
frequency between 150 kHz and 200 kHz.
frequency between 150 kHz and 200 kHz.