Freescale Semiconductor MCF52211 ユーザーズマニュアル
Pulse-Width Modulation (PWM) Module
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
27-4
Freescale Semiconductor
27.2.2
PWM Polarity Register (PWMPOL)
The starting polarity of each PWM channel waveform is determined by the associated PWMPOL[PPOLn]
bit. If the polarity is changed while a PWM signal is being generated, a truncated or stretched pulse can
occur during the transition.
bit. If the polarity is changed while a PWM signal is being generated, a truncated or stretched pulse can
occur during the transition.
27.2.3
PWM Clock Select Register (PWMCLK)
Each PWM channel has the capability of selecting one of two clocks. For channels0, 1, 4, and 5, the clock
choices are clock A or SA. For channels2, 3, 6, and 7, the choices are clock B or SB. The clock selection
is done with the below PWMCLK[PCLKn] control bits. If a clock select is changed while a PWM signal
is being generated, a truncated or stretched pulse can occur during the transition.
choices are clock A or SA. For channels2, 3, 6, and 7, the choices are clock B or SB. The clock selection
is done with the below PWMCLK[PCLKn] control bits. If a clock select is changed while a PWM signal
is being generated, a truncated or stretched pulse can occur during the transition.
1
PWME1
PWM Channel 1 Output Enable. If enabled, the PWM signal becomes available at PWMOUT1 when its
corresponding clock source begins its next cycle.
0 PWM output disabled
1 PWM output enabled
corresponding clock source begins its next cycle.
0 PWM output disabled
1 PWM output enabled
0
PWME0
PWM Channel 0 Output Enable. If enabled, the PWM signal becomes available at PWMOUT0 when its
corresponding clock source begins its next cycle. If PWMCTL[CON01] is set, then this bit has no effect and
PWMOUT0 is disabled.
0 PWM output disabled
1 PWM output enabled, if PWMCTL[CON01]=0
corresponding clock source begins its next cycle. If PWMCTL[CON01] is set, then this bit has no effect and
PWMOUT0 is disabled.
0 PWM output disabled
1 PWM output enabled, if PWMCTL[CON01]=0
IPSBAR
Offset:
0x1B_0001 (PWMPOL)
Access: User Read/Write
7
6
5
4
3
2
1
0
R
PPOL7
PPOL6
PPOL5
PPOL4
PPOL3
PPOL2
PPOL1
PPOL0
W
Reset:
0
0
0
0
0
0
0
0
Figure 27-3. PWM Polarity Register (PWMPOL)
Table 27-3. PWMPOL Field Descriptions
Field
Description
7–0
PPOLn
PWM Channel n Polarity. The even-numbered channels’ polarity has no effect when the corresponding
PWMCTL[CONn(n+1)] bit is set. For example, if PWMCTL[CON01] equals 1, PWMPOL[PPOL0] has no affect.
0 PWM channel n output is low at the beginning of the period, then goes high when the duty count is reached
1 PWM channel n output is high at the beginning of the period, then goes low when the duty count is reached
PWMCTL[CONn(n+1)] bit is set. For example, if PWMCTL[CON01] equals 1, PWMPOL[PPOL0] has no affect.
0 PWM channel n output is low at the beginning of the period, then goes high when the duty count is reached
1 PWM channel n output is high at the beginning of the period, then goes low when the duty count is reached
Table 27-2. PWME Field Descriptions (continued)
Field
Description