Fujitsu FR20 ユーザーズマニュアル
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CHAPTER 1 Overview of MB91191/MB91192 Series
1.1
Feature of MB91191/MB91192 Series
The MB91191/MB91192 series is a single-chip microcontroller with a built-in peripheral I/
O resource suited to software servo control of VTRs that require high-speed CPU
processing, featuring a 32-bit RISC-CPU (FR20 series) at its core.
O resource suited to software servo control of VTRs that require high-speed CPU
processing, featuring a 32-bit RISC-CPU (FR20 series) at its core.
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Feature of MB91191/MB91192 Series
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CPU
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32-bit RISC (FR20), load/store architecture, 5 stages pipeline
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32-bit general-purpose register x 16
•
One instruction/one cycle, 16-bit fixed length instructions (basic instruction)
•
Commands for memory to memory transfer, bit processing, and barrel shift, etc.: Commands suitable for
embedded applications
embedded applications
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Commands for function entry/exit, command for multi loading/storing of register contents: Commands
supporting high-level languages
supporting high-level languages
•
Register interlock function: Simplification of assembler description
•
Branch instruction with a delay slot: Decrease of overhead for branch processing
•
Support at internal into/instruction level of multipliers
- 32-bit multiplication with sign: 5 cycles
- 16-bit multiplication with sign: 3 cycles
•
Interruption (save of PC and PS): 6 cycles and 16 priority levels
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Bus interface
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16-bit address output, 8-/16-bit data I/O
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Basic bus cycle: 2 clock cycle
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Support interface to various memories
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Multiplexed data/address input/output
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Auto-wait cycle: 0 to 7 cycles can be set randomly per area.
•
Unused data and address pins can be used as I/O ports.
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Support of little endian mode
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Bit search module
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1-cycle search for the change bit position of the first 1/0 from the MSB within a word
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Serial I/O
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Internal buffer RAM x 3ch (up to 128 bytes can be transferred automatically)
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Independent mode of the transmission/reception buffer (up to 64 bytes can be transferred automatically)
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A/D converter (Successive Approximation Type)
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10-bit x 16ch
•
Successive approximation conversion method (conversion time: 8.4
µs @20MHz)
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Channel scan function
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Hardware and software conversion start functions
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Internal FIFO (Software conversion: 6 stages, Hardware conversion: 6 stages)