Intel 8XC196NP ユーザーズマニュアル
8XC196NP, 80C196NU USER’S MANUAL
6-16
INT_PEND
Address:
Reset State:
0009H
00H
When hardware detects a pending interrupt, it sets the corresponding bit in the interrupt pending
(INT_PEND or INT_PEND1) registers. When the vector is taken, the hardware clears the pending bit.
Software can generate an interrupt by setting the corresponding interrupt pending bit.
(INT_PEND or INT_PEND1) registers. When the vector is taken, the hardware clears the pending bit.
Software can generate an interrupt by setting the corresponding interrupt pending bit.
7
0
EPA0
RI
TI
EXTINT1
EXTINT0
—
OVRTM2
OVRTM1
Bit
Number
Function
7:3
1:0
1:0
Any set bit indicates that the corresponding interrupt is pending. The interrupt bit is
cleared when processing transfers to the corresponding interrupt vector.
cleared when processing transfers to the corresponding interrupt vector.
The standard interrupt vector locations are as follows:
Bit Mnemonic
Interrupt
Standard Vector
EPA0
EPA Capture/Compare Channel 0
FF200EH
RI
SIO Receive
FF200CH
TI
SIO Transmit
FF200AH
EXTINT1
EXTINT1 pin
FF2008H
EXTINT0
EXTINT0 pin
FF2006H
OVRTM2
Timer 2 Overflow/Underflow
FF2002H
OVRTM1
Timer 1 Overflow/Underflow
FF2000H
2
Reserved. This bit is undefined.
Figure 6-7. Interrupt Pending (INT_PEND) Register