Intel 8XC196NP ユーザーズマニュアル
7-2
8XC196NP, 80C196NU USER’S MANUAL
Table 7-3 lists the registers associated with the bidirectional ports. Each port has three control reg-
isters (Px_MODE, Px_DIR, and Px_REG); they can be both read and written. The Px_PIN regis-
ter is a status register that returns the logic level present on the pins; it can only be read. The
registers are byte-addressable and can be windowed.“Bidirectional Port Considerations” on page
7-9 discusses special considerations for reading P2_REG.7.
isters (Px_MODE, Px_DIR, and Px_REG); they can be both read and written. The Px_PIN regis-
ter is a status register that returns the logic level present on the pins; it can only be read. The
registers are byte-addressable and can be windowed.“Bidirectional Port Considerations” on page
7-9 discusses special considerations for reading P2_REG.7.
Table 7-2. Bidirectional Port Pins
Port Pin
Special-function
Signal(s)
Special-function
Signal Type
Associated
Peripheral
P1.0
EPA0
I/O
EPA
P1.1
EPA1
I/O
EPA
P1.2
EPA2
I/O
EPA
P1.3
EPA3
I/O
EPA
P1.4
T1CLK
I
Timer 1
P1.5
T1DIR
I
Timer 1
P1.6
T2CLK
I
Timer 2
P1.7
T2DIR
I
Timer 2
P2.0
TXD
O
SIO
P2.1
RXD
I/O
SIO
P2.2
EXTINT0
I
Interrupts
P2.3
BREQ#
O
Bus controller
P2.4
EXTINT1
I
Interrupts
P2.5
HOLD#
I
Bus controller
P2.6
HLDA#
O
Bus controller
P2.7
CLKOUT
O
Clock generator
P3.0
CS0#
O
Chip-select unit
P3.1
CS1#
O
Chip-select unit
P3.2
CS2#
O
Chip-select unit
P3.3
CS3#
O
Chip-select unit
P3.4
CS4#
O
Chip-select unit
P3.5
CS5#
O
Chip-select unit
P3.6
EXTINT2
I
Interrupts
P3.7
EXTINT3
I
Interrupts
P4.0
PWM0
O
PWM
P4.1
PWM1
O
PWM
P4.2
PWM2
O
PWM
P4.3
—
I/O
—