Intel 8XC196MD ユーザーズマニュアル
8XC196MC, MD, MH USER’S MANUAL
13-12
13.6.2 Issuing the Reset (RST) Instruction
The RST instruction (opcode FFH) resets the device by pulling RESET# low for 16 state times.
It also clears the processor status word (PSW), sets the master program counter (PC) to 2080H,
and resets the special function registers (SFRs). See Table C-2 on page C-2 for the reset values
of the SFRs.
It also clears the processor status word (PSW), sets the master program counter (PC) to 2080H,
and resets the special function registers (SFRs). See Table C-2 on page C-2 for the reset values
of the SFRs.
Putting pull-ups on the address/data bus causes unimplemented areas of memory to be read as
FFH. If unused internal OTPROM memory is set to FFH, then execution from any unused mem-
ory locations will reset the device.
FFH. If unused internal OTPROM memory is set to FFH, then execution from any unused mem-
ory locations will reset the device.
13.6.3 Issuing an Illegal IDLPD Key Operand
The device resets itself if an illegal key operand is used with the idle/powerdown (IDLPD) com-
mand. The legal keys are “1” for idle mode and “2” for powerdown mode. If any other value is
used, the device executes a reset sequence. (See Appendix A for a description of the IDLPD com-
mand.)
mand. The legal keys are “1” for idle mode and “2” for powerdown mode. If any other value is
used, the device executes a reset sequence. (See Appendix A for a description of the IDLPD com-
mand.)
13.6.4 Generating Wait States
The 8XC196Mx devices can interface with a variety of external memory devices. With slower
external devices this requires inserting wait states to lengthen the bus cycle. An external device
can use the READY input to request wait states in addition to the wait states that are generated
internally by the 8XC196Mx device. The READY signal must be held valid until the T
external devices this requires inserting wait states to lengthen the bus cycle. An external device
can use the READY input to request wait states in addition to the wait states that are generated
internally by the 8XC196Mx device. The READY signal must be held valid until the T
CLYX
(for
the 8XC196MC, MD) or T
LLYX
(for the 8XC196MH) timing specification is met. Do not exceed
the maximum T
CLYX
(for the 8XC196MC, MD) or T
LLYX
(for the 8XC196MH) specification or
additional (unwanted) wait states might be added (see Chapter 15, “Wait States (Ready Control),”
for a detailed explanation).
for a detailed explanation).
13.6.5 Enabling the Watchdog Timer
The watchdog timer (WDT) is a 16-bit counter that resets the device when the counter overflows.
The WDE bit (bit 3) of CCR1 controls whether the watchdog is enabled immediately or is dis-
abled until the first time it is cleared. Clearing WDE activates the watchdog. Setting WDE makes
the watchdog timer inactive, but you can activate it by clearing the watchdog register. Once the
watchdog is activated, only a reset can disable it.
The WDE bit (bit 3) of CCR1 controls whether the watchdog is enabled immediately or is dis-
abled until the first time it is cleared. Clearing WDE activates the watchdog. Setting WDE makes
the watchdog timer inactive, but you can activate it by clearing the watchdog register. Once the
watchdog is activated, only a reset can disable it.
The 8XC196MC and 8XC196MD allow only one reset interval, 64K state times. This requires
your software to interrupt itself every 65,535 state times to reset the watchdog. The 8XC196MH
allows you to choose a longer interval.
your software to interrupt itself every 65,535 state times to reset the watchdog. The 8XC196MH
allows you to choose a longer interval.