Intel Embedded Microcontroller ユーザーズマニュアル
3-5
ADDRESS SPACES
The 64-Kbyte external data memory for MCS 51 microcontrollers is mapped into the memory
region specified by bits 16–23 of the data pointer DPX, i.e., DPXL. DPXL is accessible as register
file location 57 and also as the SFR at S:084H (see “Dedicated Registers” on page 3-13). The re-
set value of DPXL is 01H, which maps the external memory to region 01: as shown in Figure 3-3.
You can change this mapping by writing a different value to DPXL. A mapping of the MCS 51
microcontroller external data memory into any 64-Kbyte memory region in the MCS 251 archi-
tecture provides complete run-time compatibility because the lower 16 address bits are identical
in the two address spaces.
region specified by bits 16–23 of the data pointer DPX, i.e., DPXL. DPXL is accessible as register
file location 57 and also as the SFR at S:084H (see “Dedicated Registers” on page 3-13). The re-
set value of DPXL is 01H, which maps the external memory to region 01: as shown in Figure 3-3.
You can change this mapping by writing a different value to DPXL. A mapping of the MCS 51
microcontroller external data memory into any 64-Kbyte memory region in the MCS 251 archi-
tecture provides complete run-time compatibility because the lower 16 address bits are identical
in the two address spaces.
The 256 bytes of on-chip data memory for MCS 51 microcontrollers (00H-FFH) are mapped to
addresses 00:0000H-00:00FFH to ensure complete run-time compatibility. In the MCS 51 archi-
tecture, the lower 128 bytes (00H-7FH) are directly and indirectly addressable; however the up-
per 128 bytes are accessible by indirect addressing only. In the MCS 251 architecture, all
locations in region 00: are accessible by direct, indirect, and displacement addressing (see
“8XC251SA, SB, SP, SQ Memory Space” on page 3-5).
addresses 00:0000H-00:00FFH to ensure complete run-time compatibility. In the MCS 51 archi-
tecture, the lower 128 bytes (00H-7FH) are directly and indirectly addressable; however the up-
per 128 bytes are accessible by indirect addressing only. In the MCS 251 architecture, all
locations in region 00: are accessible by direct, indirect, and displacement addressing (see
“8XC251SA, SB, SP, SQ Memory Space” on page 3-5).
The 128-byte SFR space for MCS 51 microcontrollers is mapped into the 512-byte SFR space of
the MCS 251 architecture starting at address S:080H, as shown in Figure 3-3. This provides com-
plete compatibility with direct addressing of MCS 51 microcontroller SFRs (including bit ad-
dressing). The SFR addresses are unchanged in the new architecture. In the MCS 251
architecture, SFRs A, B, DPL, DPH, and SP (as well as the new SFRs DPXL and SPH) reside in
the register file for high performance. However, to maintain compatibility, they are also mapped
into the SFR space at the same addresses as in the MCS 51 architecture.
the MCS 251 architecture starting at address S:080H, as shown in Figure 3-3. This provides com-
plete compatibility with direct addressing of MCS 51 microcontroller SFRs (including bit ad-
dressing). The SFR addresses are unchanged in the new architecture. In the MCS 251
architecture, SFRs A, B, DPL, DPH, and SP (as well as the new SFRs DPXL and SPH) reside in
the register file for high performance. However, to maintain compatibility, they are also mapped
into the SFR space at the same addresses as in the MCS 51 architecture.
3.2
8XC251SA, SB, SP, SQ MEMORY SPACE
Figure 3-4 shows the logical memory space for the 8XC251Sx microcontroller. The usable mem-
ory space of the 8XC251Sx consists of four 64-Kbyte regions: 00:, 01:, FE:, and FF:. Code can
execute from all four regions; code execution begins at FF:0000H. Regions 02:–FD: are reserved.
Reading a location in the reserved area returns an unspecified value. Software can execute a write
to the reserved area, but nothing is actually written.
ory space of the 8XC251Sx consists of four 64-Kbyte regions: 00:, 01:, FE:, and FF:. Code can
execute from all four regions; code execution begins at FF:0000H. Regions 02:–FD: are reserved.
Reading a location in the reserved area returns an unspecified value. Software can execute a write
to the reserved area, but nothing is actually written.
All four regions of the memory space are available at the same time. The maximum number of
external address lines is 18, which limits external memory to a maximum of four regions (256
Kbytes). See “Configuring the External Memory Interface” on page 4-8 and “External Memory
Design Examples” on page 13-18.
external address lines is 18, which limits external memory to a maximum of four regions (256
Kbytes). See “Configuring the External Memory Interface” on page 4-8 and “External Memory
Design Examples” on page 13-18.