Intel 80C196NU ユーザーズマニュアル
8-6
8XC196NP, 80C196NU USER’S MANUAL
When the serial port is configured for mode 1, 2, or 3, writing to SBUF_TX causes the serial port
to start transmitting data. New data placed in SBUF_TX is transmitted only after the stop bit of
the previous data has been sent. A falling edge on the RXD input causes the serial port to begin
receiving data if RXD is enabled. Disabling RXD stops a reception in progress and inhibits fur-
ther receptions. (See “Programming the Control Register” on page 8-8.)
to start transmitting data. New data placed in SBUF_TX is transmitted only after the stop bit of
the previous data has been sent. A falling edge on the RXD input causes the serial port to begin
receiving data if RXD is enabled. Disabling RXD stops a reception in progress and inhibits fur-
ther receptions. (See “Programming the Control Register” on page 8-8.)
8.3.2.1
Mode 1
Mode 1 is the standard asynchronous communications mode. The data frame used in this mode
(Figure 8-4) consists of ten bits: a start bit (0), eight data bits (LSB first), and a stop bit (1). If
parity is enabled, a parity bit is sent instead of the eighth data bit, and parity is checked on recep-
tion.
(Figure 8-4) consists of ten bits: a start bit (0), eight data bits (LSB first), and a stop bit (1). If
parity is enabled, a parity bit is sent instead of the eighth data bit, and parity is checked on recep-
tion.
Figure 8-4. Serial Port Frames for Mode 1
The transmit and receive functions are controlled by separate shift clocks. The transmit shift
clock starts when the baud-rate generator is initialized. The receive shift clock is reset when a start
bit (high-to-low transition) is received. Therefore, the transmit clock may not be synchronized
with the receive clock, although both will be at the same frequency.
clock starts when the baud-rate generator is initialized. The receive shift clock is reset when a start
bit (high-to-low transition) is received. Therefore, the transmit clock may not be synchronized
with the receive clock, although both will be at the same frequency.
The transmit interrupt (TI) and receive interrupt (RI) flags in SP_STATUS are set to indicate com-
pleted operations. During a reception, both the RI flag and the RI interrupt pending bit are set just
before the end of the stop bit. During a transmission, both the TI flag and the TI interrupt pending
bit are set at the beginning of the stop bit. The next byte cannot be sent until the stop bit is sent.
pleted operations. During a reception, both the RI flag and the RI interrupt pending bit are set just
before the end of the stop bit. During a transmission, both the TI flag and the TI interrupt pending
bit are set at the beginning of the stop bit. The next byte cannot be sent until the stop bit is sent.
Use caution when connecting more than two devices with the serial port in half-duplex (i.e., with
one wire for transmit and receive). The receiving processor must wait for one bit time after the
RI flag is set before starting to transmit. Otherwise, the transmission could corrupt the stop bit,
causing a problem for other devices listening on the link.
one wire for transmit and receive). The receiving processor must wait for one bit time after the
RI flag is set before starting to transmit. Otherwise, the transmission could corrupt the stop bit,
causing a problem for other devices listening on the link.
Start
Stop
D0
D1
D2
D3
D4
D5
D6
D7
Stop
8 Bits of Data or 7 Bits of Data
with Parity Bit
10-Bit Frame
A0245-02