Intel 80C196NU ユーザーズマニュアル
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8XC196NP, 80C196NU USER’S MANUAL
Chapter 8 — Serial I/O (SIO) Port — describes the asynchronous/synchronous serial I/O (SIO)
port and explains how to program it.
port and explains how to program it.
Chapter 9 —Pulse-width Modulator — provides a functional overview of the pulse width mod-
ulator (PWM) modules, describes how to program them, and provides sample circuitry for con-
verting the PWM outputs to analog signals.
ulator (PWM) modules, describes how to program them, and provides sample circuitry for con-
verting the PWM outputs to analog signals.
Chapter 10 — Event Processor Array (EPA) — describes the event processor array, a tim-
er/counter-based, high-speed input/output unit. It describes the timer/counters and explains how
to program the EPA and how to use the EPA to produce pulse-width modulated (PWM) outputs.
er/counter-based, high-speed input/output unit. It describes the timer/counters and explains how
to program the EPA and how to use the EPA to produce pulse-width modulated (PWM) outputs.
Chapter 11 — Minimum Hardware Considerations — describes options for providing the ba-
sic requirements for device operation within a system, discusses other hardware considerations,
and describes device reset options.
sic requirements for device operation within a system, discusses other hardware considerations,
and describes device reset options.
Chapter 12 — Special Operating Modes — provides an overview of the idle, powerdown,
standby, and on-circuit emulation (ONCE) modes and describes how to enter and exit each mode.
standby, and on-circuit emulation (ONCE) modes and describes how to enter and exit each mode.
Chapter 13 — Interfacing with External Memory — lists the external memory signals and de-
scribes the registers that control the external memory interface. It discusses the chip selects, mul-
tiplexed and demultiplexed bus modes, bus width and memory configurations, the bus-hold
protocol, write-control modes, and internal wait states and ready control. Finally, it provides tim-
ing information for the system bus.
scribes the registers that control the external memory interface. It discusses the chip selects, mul-
tiplexed and demultiplexed bus modes, bus width and memory configurations, the bus-hold
protocol, write-control modes, and internal wait states and ready control. Finally, it provides tim-
ing information for the system bus.
Appendix A — Instruction Set Reference — provides reference information for the instruction
set. It describes each instruction; defines the processor status word (PSW) flags; shows the rela-
tionships between instructions and PSW flags; and lists hexadecimal opcodes, instruction
lengths, and execution times. (For additional information about the instruction set, see Chapter 4,
“Programming Considerations.”)
set. It describes each instruction; defines the processor status word (PSW) flags; shows the rela-
tionships between instructions and PSW flags; and lists hexadecimal opcodes, instruction
lengths, and execution times. (For additional information about the instruction set, see Chapter 4,
“Programming Considerations.”)
Appendix B — Signal Descriptions — provides reference information for the device pins, in-
cluding descriptions of the pin functions, reset status of the I/O and control pins, and package pin
assignments.
cluding descriptions of the pin functions, reset status of the I/O and control pins, and package pin
assignments.
Appendix C — Registers — provides a compilation of all device special-function registers
(SFRs) arranged alphabetically by register mnemonic. It also includes tables that list the win-
dowed direct addresses for all SFRs in each possible window.
(SFRs) arranged alphabetically by register mnemonic. It also includes tables that list the win-
dowed direct addresses for all SFRs in each possible window.
Glossary — defines terms with special meaning used throughout this manual.
Index — lists key topics with page number references.