Intel 80C196NU ユーザーズマニュアル
8XC196NP, 80C196NU USER’S MANUAL
11-4
11.2 APPLYING AND REMOVING POWER
When power is first applied to the device, RESET# must remain continuously low for at least one
state time after the power supply is within tolerance and the oscillator/clock has stabilized; oth-
erwise, operation might be unpredictable. Similarly, when powering down a system, RESET#
should be brought low before V
state time after the power supply is within tolerance and the oscillator/clock has stabilized; oth-
erwise, operation might be unpredictable. Similarly, when powering down a system, RESET#
should be brought low before V
CC
is removed; otherwise, an inadvertent write to an external lo-
cation might occur. Carefully evaluate the possible effect of power-up and power-down sequenc-
es on a system.
es on a system.
11.3 NOISE PROTECTION TIPS
The fast rise and fall times of high-speed CMOS logic often produce noise spikes on the power
supply lines and outputs. To minimize noise, it is important to follow good design and board lay-
out techniques. We recommend liberal use of decoupling capacitors and transient absorbers. Add
0.01 µF bypass capacitors between V
supply lines and outputs. To minimize noise, it is important to follow good design and board lay-
out techniques. We recommend liberal use of decoupling capacitors and transient absorbers. Add
0.01 µF bypass capacitors between V
CC
and each V
SS
pin to reduce noise (Figure 11-2). Place the
capacitors as close to the device as possible. Use the shortest possible path to connect V
SS
lines
to ground and each other.
Figure 11-2. Power and Return Connections
8XC196 Device
CC
V
SS
V
SS
V
SS
V
+5 V
5 V
Return
Power Source
†
†
†
Use 0.01 µF bypass capacitors for maximum decoupling.
Digital
Ground
Plane
A3069-01
8XC196 Device
+5 V
5 V
Return
Power Source
†
†
†
Use 0.01 µF bypass capacitors for maximum decoupling.
Digital
Ground
Plane
A3069-01
V
CC
V
SS
V
SS
V
SS