Intel 80C196NU ユーザーズマニュアル
8XC196NP, 80C196NU USER’S MANUAL
4-8
LD
AX,[BX]
; AX
←
MEM_WORD(BX)
ADDB AL,BL,[CX]
; AL
←
BL + MEM_BYTE(CX)
POP
[AX]
; MEM_WORD(AX)
←
MEM_WORD(SP)
; SP
←
SP + 2
4.2.3.1
Extended Indirect Addressing
Extended load and store instructions can use indirect addressing. The only difference is that the
register containing the indirect address must be a word-aligned 24-bit register to allow access to
the entire 1-Mbyte address space. The following instructions use extended indirect addressing:
register containing the indirect address must be a word-aligned 24-bit register to allow access to
the entire 1-Mbyte address space. The following instructions use extended indirect addressing:
ELD
AX,[EX]
; AX
←
MEM_WORD(EX)
ELDB AL,[EX]
; AL
←
MEM_BYTE(EX)
EST
AX,[EX]
; MEM_WORD(EX)
←
AX
ESTB AL,[EX]
; MEM_BYTE(EX)
←
AL
4.2.3.2
Indirect Addressing with Autoincrement
You can choose to automatically increment the indirect address after the current access. You spec-
ify autoincrementing by adding a plus sign (+) to the end of the indirect reference. In this case,
the instruction automatically increments the indirect address (by one if the destination is an 8-bit
register or by two if it is a 16-bit register). When your code is assembled, the assembler automat-
ically sets the least-significant bit of the indirect address register. The following instructions use
indirect addressing with autoincrement:
ify autoincrementing by adding a plus sign (+) to the end of the indirect reference. In this case,
the instruction automatically increments the indirect address (by one if the destination is an 8-bit
register or by two if it is a 16-bit register). When your code is assembled, the assembler automat-
ically sets the least-significant bit of the indirect address register. The following instructions use
indirect addressing with autoincrement:
LD
AX,[BX]+
; AX
←
MEM_WORD(BX)
; BX
←
BX + 2
ADDB AL,BL,[CX]+
; AL
←
BL + MEM_BYTE(CX)
; CX
←
CX + 1
PUSH [AX]+
; SP
←
SP - 2
; MEM_WORD(SP)
←
MEM_WORD(AX)
; AX
←
AX + 2
4.2.3.3
Extended Indirect Addressing with Autoincrement
The extended load and store instructions can also use indirect addressing with autoincrement. The
only difference is that the register containing the indirect address must be a word-aligned 24-bit
register to allow access to the entire 1-Mbyte address space. The following instructions use ex-
tended indirect addressing with autoincrement:
only difference is that the register containing the indirect address must be a word-aligned 24-bit
register to allow access to the entire 1-Mbyte address space. The following instructions use ex-
tended indirect addressing with autoincrement:
ELD
AX,[EX]+
; AX
←
MEM_WORD(EX)
; EX
←
EX + 2
ELDB AL,[EX]+
; AL
←
MEM_BYTE(EX)
; EX
←
EX + 2
EST
AX,[EX]+
; MEM_WORD(EX)
←
AX
; MEM_WORD(EX)
←
MEM_WORD(EX + 2)
ESTB AL,[EX]+
; MEM_BYTE(EX)
←
AL
; MEM_BYTE(EX)
←
MEM_BYTE(EX + 2)