Intel 80C196NU ユーザーズマニュアル
5-7
MEMORY PARTITIONS
5.2.2.3
Reserved Memory Locations
Several memory locations are reserved for testing or for use in future products. Do not read or
write these locations except to initialize them to the values shown in Table 5-3. The function or
contents of these locations may change in future revisions; software that uses reserved locations
may not function properly.
write these locations except to initialize them to the values shown in Table 5-3. The function or
contents of these locations may change in future revisions; software that uses reserved locations
may not function properly.
5.2.2.4
Interrupt and PTS Vectors
The peripheral transaction server (PTS) vectors contain the addresses of the PTS control blocks.
The upper and lower interrupt vectors contain the addresses of the interrupt service routines. See
Chapter 6, “Standard and PTS Interrupts,” for more information.
The upper and lower interrupt vectors contain the addresses of the interrupt service routines. See
Chapter 6, “Standard and PTS Interrupts,” for more information.
5.2.2.5
Chip Configuration Bytes
The chip configuration bytes (CCB0 and CCB1) specify the operating environment. They specify
the bus width, bus mode (multiplexed or demultiplexed), write-control mode, wait states, power-
down enabling, and the operating mode (1-Mbyte or 64-Kbyte mode). For the 83C196NP, CCB1
also controls ROM remapping. For the 80C196NP and 80C196NU, the CCBs are stored in exter-
nal memory (locations F2018–F201AH). For the 83C196NP, the CCBs can be stored either in ex-
ternal memory (locations F2018–F201AH) or in the on-chip ROM (locations FF2018–
FF201AH).
the bus width, bus mode (multiplexed or demultiplexed), write-control mode, wait states, power-
down enabling, and the operating mode (1-Mbyte or 64-Kbyte mode). For the 83C196NP, CCB1
also controls ROM remapping. For the 80C196NP and 80C196NU, the CCBs are stored in exter-
nal memory (locations F2018–F201AH). For the 83C196NP, the CCBs can be stored either in ex-
ternal memory (locations F2018–F201AH) or in the on-chip ROM (locations FF2018–
FF201AH).
The chip configuration bytes are the first bytes fetched from memory when the device leaves the
reset state. The post-reset sequence loads the CCBs into the chip configuration registers (CCRs).
Once they are loaded, the CCRs cannot be changed until the next device reset. Typically, the
CCBs are programmed once when the user program is compiled and are not redefined during nor-
mal operation. “Chip Configuration Registers and Chip Configuration Bytes” on page 13-14 de-
scribes the CCBs and CCRs.
reset state. The post-reset sequence loads the CCBs into the chip configuration registers (CCRs).
Once they are loaded, the CCRs cannot be changed until the next device reset. Typically, the
CCBs are programmed once when the user program is compiled and are not redefined during nor-
mal operation. “Chip Configuration Registers and Chip Configuration Bytes” on page 13-14 de-
scribes the CCBs and CCRs.
5.2.3
Peripheral Special-function Registers (SFRs)
Locations 1F00–1FFFH provide access to the peripheral SFRs (see Table 5-5). Locations in this
range that are omitted from the table are reserved. The peripheral SFRs are I/O control registers;
they are physically located in the on-chip peripherals. Peripheral SFRs can be windowed and they
can be addressed either as words or bytes, except as noted in the table.
range that are omitted from the table are reserved. The peripheral SFRs are I/O control registers;
they are physically located in the on-chip peripherals. Peripheral SFRs can be windowed and they
can be addressed either as words or bytes, except as noted in the table.