Intel 80C196NU ユーザーズマニュアル
5-11
MEMORY PARTITIONS
5.2.4.1
General-purpose Register RAM
The lower register file contains general-purpose register RAM. The stack pointer locations can
also be used as general-purpose register RAM when stack operations are not being performed.
The RALU can access this memory directly, using direct addressing.
also be used as general-purpose register RAM when stack operations are not being performed.
The RALU can access this memory directly, using direct addressing.
The upper register file also contains general-purpose register RAM. The RALU normally uses
indirect or indexed addressing to access the RAM in the upper register file. Windowing enables
the RALU to use direct addressing to access this memory. (See Chapter 4, “Programming Con-
siderations,” for a discussion of addressing modes.) Windowing provides fast context switching
of interrupt tasks and faster program execution. (See “Windowing” on page 5-13.) PTS control
blocks and the stack are most efficient when located in the upper register file.
indirect or indexed addressing to access the RAM in the upper register file. Windowing enables
the RALU to use direct addressing to access this memory. (See Chapter 4, “Programming Con-
siderations,” for a discussion of addressing modes.) Windowing provides fast context switching
of interrupt tasks and faster program execution. (See “Windowing” on page 5-13.) PTS control
blocks and the stack are most efficient when located in the upper register file.
5.2.4.2
Stack Pointer (SP)
Memory locations 0018H and 0019H contain the stack pointer (SP). The SP contains the address
of the stack. The SP must point to a word (even) address that is two bytes (for 64-Kbyte mode)
or four bytes (for 1-Mbyte mode) greater than the desired starting address. Before the CPU exe-
cutes a subroutine call or interrupt service routine, it decrements the SP (by two in 64-Kbyte
mode; by four in 1-Mbyte mode). Next, it copies (PUSHes) the address of the next instruction
from the program counter onto the stack. It then loads the address of the subroutine or interrupt
service routine into the program counter. When it executes the return-from-subroutine (RET) in-
struction at the end of the subroutine or interrupt service routine, the CPU loads (POPs) the con-
tents of the top of the stack (that is, the return address) into the program counter. Finally, it
increments the SP (by two in 64-Kbyte mode; by four in 1-Mbyte mode).
of the stack. The SP must point to a word (even) address that is two bytes (for 64-Kbyte mode)
or four bytes (for 1-Mbyte mode) greater than the desired starting address. Before the CPU exe-
cutes a subroutine call or interrupt service routine, it decrements the SP (by two in 64-Kbyte
mode; by four in 1-Mbyte mode). Next, it copies (PUSHes) the address of the next instruction
from the program counter onto the stack. It then loads the address of the subroutine or interrupt
service routine into the program counter. When it executes the return-from-subroutine (RET) in-
struction at the end of the subroutine or interrupt service routine, the CPU loads (POPs) the con-
tents of the top of the stack (that is, the return address) into the program counter. Finally, it
increments the SP (by two in 64-Kbyte mode; by four in 1-Mbyte mode).
Table 5-6. Register File Memory Addresses
Address
Range
Description
Addressing Modes
03FFH
0100H
0100H
General-purpose register RAM; upper register file
Indirect, indexed, windowed direct
00FFH
001AH
001AH
General-purpose register RAM; lower register file
Direct, indirect, indexed
0019H
0018H
0018H
Stack pointer (SP); lower register file
Direct, indirect, indexed
0017H
0000H
0000H
CPU special-function registers (SFRs); lower register file
Direct, indirect, indexed