Intel 80C196NU ユーザーズマニュアル
5-23
MEMORY PARTITIONS
5.5
FETCHING CODE AND DATA IN THE 1-MBYTE AND 64-KBYTE MODES
This section describes how the device fetches instructions and accesses data in the 1-Mbyte and
64-Kbyte modes. When the device leaves reset, the MODE64 bit (CCB1.1) selects the 1-Mbyte
or 64-Kbyte mode. The mode cannot be changed until the next reset.
64-Kbyte modes. When the device leaves reset, the MODE64 bit (CCB1.1) selects the 1-Mbyte
or 64-Kbyte mode. The mode cannot be changed until the next reset.
NOTE
The 8XC196NP and 80C196NU have two major differences concerning code
and data fetches. The 8XC196NP’s prefetch queue is four bytes, while the
80C196NU’s is eight bytes. The 8XC196NP gives higher priority to
instruction fetches than to data fetches, while the 80C196NU gives higher
priority to data accesses than to instruction fetches.
and data fetches. The 8XC196NP’s prefetch queue is four bytes, while the
80C196NU’s is eight bytes. The 8XC196NP gives higher priority to
instruction fetches than to data fetches, while the 80C196NU gives higher
priority to data accesses than to instruction fetches.
5.5.1
Fetching Instructions
The 24-bit program counter (Figure 5-7) consists of the 8-bit extended program counter (EPC)
concatenated with the 16-bit master program counter (PC). It holds the address of the next in-
struction to be fetched. The page number of the instruction is in the EPC. In 1-Mbyte mode, the
EPC can have any 8-bit value. However, only the four LSBs of the EPC are implemented exter-
nally, as EPORT pins A19:16. This means that in the 1-Mbyte mode, the device can fetch code
from any page in the 1-Mbyte address space: 00H–0FH and FFH (FFH overlays 0FH). In 64-
Kbyte mode, the EPC is fixed at FFH, which limits program memory to page FFH (and 0FH).
concatenated with the 16-bit master program counter (PC). It holds the address of the next in-
struction to be fetched. The page number of the instruction is in the EPC. In 1-Mbyte mode, the
EPC can have any 8-bit value. However, only the four LSBs of the EPC are implemented exter-
nally, as EPORT pins A19:16. This means that in the 1-Mbyte mode, the device can fetch code
from any page in the 1-Mbyte address space: 00H–0FH and FFH (FFH overlays 0FH). In 64-
Kbyte mode, the EPC is fixed at FFH, which limits program memory to page FFH (and 0FH).
Figure 5-7. The 24-bit Program Counter
5.5.2
Accessing Data
Internally, data addresses have 24 bits (Figure 5-8 on page 5-24). The lower 16 bits are supplied
by the 16-bit data address register. The upper 8 bits (the page number) come from different sourc-
es for nonextended and extended instructions. (“EPORT Operation” on page 7-12 describes how
the page number is output to the EPORT pins.)
by the 16-bit data address register. The upper 8 bits (the page number) come from different sourc-
es for nonextended and extended instructions. (“EPORT Operation” on page 7-12 describes how
the page number is output to the EPORT pins.)
A2513-03
EPC
PC
23
16 15
0