Intel 8XC196MH ユーザーズマニュアル
A-49
INSTRUCTION SET REFERENCE
Stack
Mnemonic
Direct
Immediate
Indirect
Indexed
(Note 1)
(Note 1)
Length
Opcode
Length
Opcode
Length
Opcode
Length
S/L
Opcode
POP 2
CC
—
—
2
CE
3/4
CF
POPA
1
F5
—
—
—
—
—
—
POPF
1
F3
—
—
—
—
—
—
PUSH 2
C8
3
C9
2
CA
3/4
CB
PUSHA
1
F4
—
—
—
—
—
—
PUSHF
1
F2
—
—
—
—
—
—
Data
Mnemonic
Direct
Immediate
Indirect
Indexed
(Note 1)
(Note 1)
Length
Opcode
Length
Opcode
Length
Opcode
Length
S/L
Opcode
BMOV
—
—
—
—
3
C1
—
—
BMOVI
—
—
—
—
3
CD
—
—
LD
3
A0
4
A1
3
A2
4/5
A3
LDB
3
B0
3
B1
3
B2
4/5
B3
LDBSE 3
BC
3
BD
3
BE
4/5
BF
LDBZE 3
AC
3
AD
3
AE
4/5
AF
ST 3
C0
—
—
3
C2
4/5
C3
STB 3
C4
—
—
3
C6
4/5
C7
XCH
3
04
—
—
—
—
4/5
0B
XCHB
3
14
—
—
—
—
4/5
1B
Jump
Mnemonic
Direct
Immediate
Indirect
Indexed
(Note 1)
(Note 1)
Length
Opcode
Length
Opcode
Length
Opcode
Length
S/L
Opcode
BR
—
—
—
—
2
E3
—
—
LJMP
—
—
—
—
—
—
—/3
E7
SJMP (Note 2)
—
—
—
—
—
—
2/—
20–27
TIJMP
4
E2
4
E2
—
—
—/4
E2
Table A-8. Instruction Lengths and Hexadecimal Opcodes (Continued)
NOTES:
1.
1.
For indexed instructions, the first column lists instruction lengths as
S
/
L
, where
S
is the short-indexed
instruction length and
L
is the long-indexed instruction length.
2.
For the SCALL and SJMP instructions, the three least-significant bits of the opcode are concatenated
with the eight bits to form an 11-bit, two’s complement offset.
with the eight bits to form an 11-bit, two’s complement offset.