ユーザーズマニュアル目次List of Figures5List of Tables7Overview111.1 General Description111.2 Features12Architecture Overview152.1 CPU Core152.1.1 Integer Unit152.1.2 Memory Management Unit162.1.3 Cache and TLB Subsystem162.1.4 Bus Controller Unit162.1.5 Floating Point Unit162.2 GeodeLink™ Control Processor162.3 GeodeLink™ Interface Units162.4 GeodeLink™ Memory Controller162.5 Graphics Processor172.6 Display Controller182.7 Video Processor182.7.1 CRT Interface182.7.2 TFT Controller182.7.3 Video Output Port182.8 Video Input Port182.9 GeodeLink™ PCI Bridge182.10 Security Block19Signal Definitions213.1 Buffer Types233.2 Bootstrap Options243.3 Ball Assignments243.4 Signal Descriptions333.4.1 System Interface Signals333.4.2 PLL Interface Signals343.4.3 Memory Interface Signals (DDR)353.4.4 Internal Test and Measurement Interface Signals363.4.5 PCI Interface Signals373.4.6 TFT Display Interface Signals403.4.7 CRT Display Interface Signals413.4.8 VIP Interface Signals413.4.9 Power and Ground Interface Signals42GeodeLink™ Interface Unit454.1 MSR Set454.1.1 Port Address464.1.2 Port Addressing Exceptions474.1.3 Memory and I/O Mapping474.1.3.1 Memory Routing and Translation474.1.3.2 I/O Routing and Translation494.1.3.3 Special Cycles494.2 GLIU Register Descriptions504.2.1 Standard GeodeLink™ Device (GLD) MSRs554.2.1.1 GLD Capabilities MSR (GLD_MSR_CAP)554.2.1.2 GLD Master Configuration MSR (GLD_MSR_CONFIG)554.2.1.3 GLD SMI MSR (GLD_MSR_SMI)564.2.1.4 GLD Error MSR (GLD_MSR_ERROR)574.2.1.5 GLD Power Management MSR (GLD_MSR_PM)594.2.1.6 GLD Diagnostic MSR (GLD_MSR_DIAG)604.2.2 GLIU Specific Registers604.2.2.1 Coherency (COH)604.2.2.2 Port Active Enable (PAE)614.2.2.3 Arbitration (ARB)624.2.2.4 Asynchronous SMI (ASMI)624.2.2.5 Asynchronous ERR (AERR)634.2.2.6 GLIU Physical Capabilities (PHY_CAP)654.2.2.7 N Outstanding Response (NOUT_RESP)664.2.2.8 N Outstanding Write Data (NOUT_WDATA)674.2.2.9 SLAVE_ONLY674.2.2.10 WHO AM I (WHOAMI)684.2.2.11 GLIU Slave Disable (GLIU_SLV)694.2.2.12 Arbitration2 (ARB2)704.2.3 GLIU Statistic and Comparator MSRs714.2.3.1 Descriptor Statistic Counter (STATISTIC_CNT[0:3])714.2.3.2 Statistic Mask (STATISTIC_MASK[0:3]724.2.3.3 Statistic Action (STATISTIC_ACTION[0:3]734.2.3.4 Request Compare Value (RQ_COMPARE_VAL[0:3]744.2.3.5 Request Compare Mask (RQ_COMPARE_MASK[0:3]754.2.3.6 DA Compare Value Low (DA_COMPARE_VAL_LO[0:3]764.2.3.7 DA Compare Value High (DA_COMPARE_VAL_HI[0:3]774.2.3.8 DA Compare Mask Low (DA_COMPARE_MASK_LO[0:3])784.2.3.9 DA Compare Mask High (DA_COMPARE_MASK_HI[0:3])794.2.4 P2D Descriptor Registers804.2.4.1 P2D Base Mask Descriptor (P2D_BM)804.2.4.2 P2D Base Mask Offset Descriptor (P2D_BMO)814.2.4.3 P2D Range Descriptor (P2D_R)824.2.4.4 P2D Range Offset Descriptor (P2D_RO)834.2.4.5 P2D Swiss Cheese Descriptor (P2D_SC)844.2.5 SPARE MSRs (SPARE_MSR[0:9], A:F)854.2.6 I/O Descriptors864.2.6.1 IOD Base Mask Descriptors (IOD_BM)864.2.6.2 IOD Swiss Cheese Descriptors (IOD_SC)87CPU Core895.1 Core Processor Initialization895.2 Instruction Set Overview905.2.1 Lock Prefix905.2.2 Register Sets905.3 Application Register Set915.3.1 General Purpose Registers925.3.2 Segment Registers925.3.3 Instruction Pointer Register925.3.4 EFLAGS Register935.4 System Register Set945.4.1 Control Registers955.5 CPU Core Register Descriptions995.5.1 Standard GeodeLink™ Device MSRs1085.5.1.1 GLD Capabilities MSR (GLD_MSR_CAP)1085.5.1.2 GLD Master Configuration MSR (GLD_MSR_CONFIG)1085.5.1.3 GLD SMI MSR (GLD_MSR_SMI)1095.5.1.4 GLD Error MSR (GLD_MSR_ERROR)1095.5.1.5 GLD Power Management MSR (GLD_MSR_PM)1095.5.1.6 GLD Diagnostic Bus Control MSR (GLD_MSR_DIAG)1095.5.2 CPU Core Specific MSRs1105.5.2.1 Time Stamp Counter MSR (TSC_MSR)1105.5.2.2 Performance Event Counter 0 MSR (PERF_CNT0_MSR)1105.5.2.3 Performance Event Counter 1 MSR (PERF_CNT1_MSR)1115.5.2.4 SYSENTER/SYSEXIT Code Segment Selector MSR (SYS_CS_MSR)1125.5.2.5 SYSENTER/SYSEXIT Stack Pointer MSR (SYS_SP_MSR)1135.5.2.6 SYSENTER/SYSEXIT Instruction Pointer MSR (SYS_IP_MSR)1135.5.2.7 Performance Event Counter 0 Select MSR (PERF_SEL0_MSR1145.5.2.8 Performance Event Counter 1 Select MSR (PERF_SEL1_MSR)1145.5.2.9 Instruction Fetch Configuration MSR (IF_CONFIG_MSR)1155.5.2.10 IF Invalidate MSR (IF_INVALIDATE_MSR)1185.5.2.11 IF Test Address MSR (IF_TEST_ADDR_MSR)1185.5.2.12 IF Test Data MSR (IF_TEST_DATA_MSR)1195.5.2.13 IF Sequential Count MRS (IF_SEQCOUNT_MSR)1225.5.2.14 IF Built-In Self-Test MSR (IF_BIST_MSR)1235.5.2.15 Exception Unit (XC) Configuration MSR (XC_CONFIG_MSR)1245.5.2.16 XC Mode MSR (XC_MODE_MSR)1255.5.2.17 XC History MSR (XC_HIST_MSR)1265.5.2.18 XC Microcode Address MSR (XC_UADDR_MSR)1275.5.2.19 ID Configuration MSR (ID_CONFIG_MSR)1275.5.2.20 SMM Control MSR (SMM_CTL_MSR)1285.5.2.21 Debug Management Interrupt (DMI) Control Register1295.5.2.22 Temporary MSRs1305.5.2.23 Segment Selector/Flags MSRs1315.5.2.24 SMM Header MSR (SMM_HDR_MSR)1325.5.2.25 DMM Header MSR (DMM_HDR_MSR)1335.5.2.26 Segment Base/Limit MSRs1345.5.2.27 Debug Registers 1 and 0 MSR (DR1_DR0_MSR)1355.5.2.28 Debug Registers 3 and 2 MSR (DR3_DR2_MSR)1355.5.2.29 Debug Registers 7 and 6 MSR (DR6_DR7_MSR)1365.5.2.30 Extended Debug Registers 1 and 0 MSR (XDR1_XDR0_MSR)1375.5.2.31 Extended Debug Registers 3 and 2 MSR (XDR3_XDR2_MSR)1375.5.2.32 Extended Debug Registers 5 and 4 MSR (XDR5_XDR4_MSR)1385.5.2.33 Extended Debug Registers 7 and 6 MSR (XDR7_XDR6_MSR)1385.5.2.34 Extended Debug Registers 9 and 8 MSR (XDR9_XDR8_MSR)1405.5.2.35 Extended Debug Registers 11 and 10 MSR (XDR11_XDR10_MSR)1415.5.2.36 EX Stage Instruction Pointer MSR (EX_IP_MSR)1415.5.2.37 WB Stage Instruction Pointer MSR (WB_IP_MSR)1425.5.2.38 EX Stage Linear Instruction Pointer MSR (EX_LIP_MSR)1425.5.2.39 WB Stage Linear Instruction Pointer MSR (WB_LIP_MSR)1435.5.2.40 C1/C0 Linear Instruction Pointer MSR (C1_C0_LIP_MSR)1435.5.2.41 C3/C2 Linear Instruction Pointer MSR (C3_C2_LIP_MSR)1445.5.2.42 Floating Point Environment Code Segment (FPENV_CS_MSR)1445.5.2.43 Floating Point Environment Instruction Pointer (FPENV_IP_MSR)1455.5.2.44 Floating Point Environment Data Segment (FPENV_DS_MSR)1455.5.2.45 Floating Point Environment Data Pointer (FPENV_DP_MSR)1465.5.2.46 Floating Point Environment Opcode Pointer (FPENV_OP_MSR)1465.5.2.47 Address Calculation Unit Configuration MSR (AC_CONFIG_MSR)1475.5.2.48 General Register MSRs1485.5.2.49 Extended Flags MSR (EFLAG_MSR)1495.5.2.50 Control Register 0 MSR (CR0_MSR)1495.5.2.51 Instruction Memory Configuration MSR (IM_CONFIG_MSR)1505.5.2.52 Instruction Cache Index MSR (IC_INDEX_MSR)1525.5.2.53 Instruction Cache Data MSR (IC_DATA_MSR)1525.5.2.54 Instruction Cache Tag (IC_TAG_MSR)1535.5.2.55 Instruction Cache Tag with Increment (IC_TAG_I_MSR)1545.5.2.56 L0 Instruction Cache Data MSR (L0_IC_DATA_MSR)1545.5.2.57 L0 Instruction Cache Tag with Increment MSR (L0_IC_TAG_I_MSR)1545.5.2.58 L1 Instruction TLB Index (ITB_INDEX_MSR)1555.5.2.59 L1 Instruction TLB Least Recently Used MSR (ITB_LRU_MSR)1565.5.2.60 L1 Instruction TLB Entry MSRs1575.5.2.61 Instruction Memory Subsystem BIST Tag MSR (IM_BIST_TAG_MSR)1585.5.2.62 Instruction Memory Subsystem BIST Data MSR (IM_BIST_DATA_MSR)1585.5.2.63 Data Memory Subsystem Configuration 0 MSR (DM_CONFIG0_MSR)1595.5.2.64 Data Memory Subsystem Configuration 1 MSR (DM_CONFIG1_MSR)1625.5.2.65 Data Memory Subsystem Prefetch Lock MSR (DM_PFLOCK_MSR)1635.5.2.66 Default Region Configuration Properties MSR (RCONF_DEFAULT_MSR)1645.5.2.67 Region Configuration Bypass MSR (RCONF_BYPASS_MSR)1655.5.2.68 Region Configuration A0000-BFFFF MSR (RCONF_A0_BF_MSR)1655.5.2.69 Region Configuration C0000-DFFFF MSR (RCONF_C0_DF_MSR)1665.5.2.70 Region Configuration E0000-FFFFF MSR (RCONF_E0_FF_MSR)1665.5.2.71 Region Configuration SMM MSR (RCONF_SMM_MSR)1675.5.2.72 Region Configuration DMM MSR (RCONF_DMM_MSR)1685.5.2.73 Region Configuration Range MSRs 0 through 71695.5.2.74 x86 Control Registers MSRs (CR1, CR2, CR3, CR4)1725.5.2.75 Data Cache Index MSR (DC_INDEX_MSR)1725.5.2.76 Data Cache Data MSR (DC_DATA_MSR)1735.5.2.77 Data Cache Tag MSR (DC_TAG_MSR)1735.5.2.78 Data Cache Tag with Increment MSR (DC_TAG_I_MSR)1745.5.2.79 Data/Instruction Cache Snoop Register (SNOOP_MSR)1755.5.2.80 L1 Data TLB Index Register (L1DTLB_INDEX_MSR)1755.5.2.81 L1 Data TLB Least Recently Used MSR (L1DTLB_LRU_MSR)1765.5.2.82 L1 Data TLB Entry MSR (L1DTLB_ENTRY_MSR)1775.5.2.83 L1 Data TLB Entry with Increment MSR (L1DTLB_ENTRY_I_MSR)1785.5.2.84 L2 TLB/DTE/PTE Index MSR (L2TLB_INDEX_MSR)1785.5.2.85 L2 TLB/DTE/PTE Least Recently Used MSR (L2TLB_LRU_MSR)1795.5.2.86 L2 TLB/DTE/PTE Entry MSR (L2TLB_ENTRY_MSR)1805.5.2.87 L2 TLB/DTE/PTE Entry with Increment MSR (L2TLB_ENTRY_I_MSR)1825.5.2.88 Data Memory Subsystem Built-In Self-Test MSR (DM_BIST_MSR)1825.5.2.89 Bus Controller Configuration 0 MSR (BC_CONFIG0_MSR)1835.5.2.90 Bus Controller Configuration 1 MSR (BC_CONFIG1_MSR)1845.5.2.91 Reserved Status MSR (RSVD_STS_MSR)1855.5.2.92 MSR Lock MSR (MSR_LOCK_MSR)1855.5.2.93 Real Time Stamp Counter MSR (RTSC_MSR)1865.5.2.94 TSC and RTSC Low DWORDs MSR (RTSC_TSC_MSR)1865.5.2.95 L2 Cache Configuration MSR (L2_CONFIG_MSR)1875.5.2.96 L2 Cache Status MSR (L2_STATUS_MSR)1885.5.2.97 L2 Cache Index MSR (L2_INDEX_MSR)1885.5.2.98 L2 Cache Data MSR (L2_DATA_MSR)1895.5.2.99 L2 Cache Tag MSR (L2_TAG_MSR)1895.5.2.100 L2 Cache Tag with Increment MSR (L2_TAG_I_MSR)1905.5.2.101 L2 Cache Built-In Self-Test MSR (L2_BIST_MSR)1905.5.2.102 L2 Cache Treatment Control MSR (L2_TRTMNT_CTL_MSR)1925.5.2.103 Power Mode MSR (PMODE_MSR)1935.5.2.104 Bus Controller Extended Debug Registers 1 and 0 MSR (BXDR1_BXDR0_MSR)1945.5.2.105 Bus Controller Extended Debug Registers 3 and 2 MSR (BXDR3_BXDR2_MSR)1945.5.2.106 Bus Controller Extended Debug Registers 6 and 7 MSR (BXDR6_BXDR7_MSR)1955.5.2.107 Bus Controller Debug Registers 0 through 3 MSRs1975.5.2.108 Bus Controller Debug Register 6 MSR (BDR6_MSR)1985.5.2.109 Bus Controller Debug Register 7 MSR (BDR7_MSR)1985.5.2.110 Memory Subsystem Array Control Enable MSR (MSS_ARRAY_CTL_EN_MSR)2005.5.2.111 Memory Subsystem Array Control 0 MSR (MSS_ARRAY_CTL0_MSR)2005.5.2.112 Memory Subsystem Array Control 1 MSR (MSS_ARRAY_CTL1_MSR)2015.5.2.113 Memory Subsystem Array Control 2 MSR (MSS_ARRAY_CTL2_MSR)2015.5.2.114 FPU Modes MSR (FP_MODE_MSR)2025.5.2.115 FPU Reserved MSR (FPU_RSVD_MSR)2025.5.2.116 FPU Reserved MSR (FPU_RSVD_MSR)2025.5.2.117 FPU x87 Control Word MSR (FPU_CW_MSR)2035.5.2.118 FPU x87 Status Word MSR (FPU_SW_MSR)2035.5.2.119 FPU x87 Tag Word MSR (FPU_TW_MSR)2035.5.2.120 FPU Busy MSR (FPU_BUSY_MSR)2045.5.2.121 FPU Register Map MSR (FPU_MAP_MSR)2045.5.2.122 Mantissa of Rx MSRs2055.5.2.123 Exponent of Rx MSRs2065.5.2.124 FPU Reserved MSRs (FPU_RSVD_MSR)2075.5.2.125 CPU ID MSRs207Integrated Functions2096.1 GeodeLink™ Memory Controller2106.1.1 Functional Hardware2116.1.1.1 Address Translation2116.1.1.2 Arbitration2156.1.1.3 Data Path2166.1.1.4 GLMC/GLCP/Pad Delay Control Settings2166.1.1.5 Basic Timing Diagrams2166.1.2 Power Control2186.1.2.1 Entry into PMode1 (Save-to-RAM)2186.1.2.2 Resume from PMode12186.1.3 BIOS Initialization Sequence2186.2 GeodeLink™ Memory Controller Register Descriptions2196.2.1 Standard GeodeLink™ Device (GLD) MSRs2206.2.1.1 GLD Capabilities MSR (GLD_MSR_CAP)2206.2.1.2 GLD Master Configuration MSR (GLD_MSR_CONFIG) - Not Used2206.2.1.3 GLD SMI MSR (GLD_MSR_SMI)2206.2.1.4 GLD Error MSR (GLD_MSR_ERROR)2216.2.1.5 GLD Power Management (GLD_MSR_PM)2226.2.1.6 GLD Diagnostic (GLD_MSR_DIAG)2226.2.2 GLMC Specific MSRs2236.2.2.1 Row Addresses Bank0 DIMM0, Bank1 DIMM0 (MC_CF_BANK01)2236.2.2.2 Row Addresses Bank2 DIMM0, Bank3 DIMM0 (MC_CF_BANK23)2236.2.2.3 Row Addresses Bank4 DIMM0, Bank5 DIMM0 (MC_CF_BANK45)2246.2.2.4 Row Addresses Bank6 DIMM0, Bank7 DIMM0 (MC_CF_BANK67)2246.2.2.5 Row Addresses Bank0 DIMM1, Bank1 DIMM0 (MC_CF_BANK89)2256.2.2.6 Row Addresses Bank2 DIMM1, Bank3 DIMM1 (MC_CF_BANKAB)2256.2.2.7 Row Addresses Bank4 DIMM1, Bank5 DIMM1 (MC_CF_BANKCD)2266.2.2.8 Row Addresses Bank6 DIMM1, Bank7 DIMM1 (MC_CF_BANKEF)2266.2.2.9 Refresh and SDRAM Program (MC_CF07_DATA)2276.2.2.10 Timing and Mode Program (MC_CF8F_DATA)2296.2.2.11 Feature Enables (MC_CF1017_DATA)2316.2.2.12 Performance Counters (MC_CFPERF_CNT1)2326.2.2.13 Counter and CAS Control (MC_PERCNT2)2336.2.2.14 Clocking and Debug (MC_CFCLK_DBUG)2336.2.2.15 Page Open Status (MC_CFPG_OPEN)2356.2.2.16 Reserved Register2356.2.2.17 PM Sensitivity Counters (MC_CF_PMCTR)2366.3 Graphics Processor2376.3.1 Command Buffer2396.3.2 Channel 32416.3.2.1 Rotating BLTs2426.3.2.2 Rotating Video2426.3.2.3 Color Depth Conversion2426.3.2.4 Palletized Color Support2436.3.2.5 Anti-Aliased Text Support2446.3.2.6 8x8 Color Pattern2446.3.2.7 Patterned Vectors2446.3.2.8 Channel 3 Host Source2456.3.2.9 Channel 3 Hints2456.3.3 BLT Operation2456.3.4 Vector Operation2466.3.5 Pipelined Operation2466.3.6 Pattern Generation2466.3.6.1 Monochrome Patterns2466.3.6.2 Color Patterns2476.3.7 8x8 Color Patterns2496.3.8 Source Data2496.3.8.1 Source Data Formats2496.3.8.2 Host Source2506.3.8.3 Source Expansion2516.3.8.4 Source Transparency2516.3.9 Destination Data2516.3.10 Raster Operations (ROP)2516.3.11 Image Compositing Using Alpha2526.4 Graphics Processor Register Definitions2546.4.1 Standard GeodeLink™ Device (GLD) MSRs2566.4.1.1 GLD Capabilities MSR (GLD_MSR_CAP)2566.4.1.2 GLD Master Configuration MSR (GLD_MSR_CONFIG)2566.4.1.3 GLD SMI MSR (GLD_MSR_SMI)2576.4.1.4 GLD Error MSR (GLD_MSR_ERROR)2576.4.1.5 GLD Power Management MSR (GLD_MSR_PM)2586.4.1.6 GLD Diagnostic MSR (GLD_MSR_DIAG)2586.4.2 Graphics Processor Configuration Registers2596.4.2.1 Destination Offset (GP_DST_OFFSET)2596.4.2.2 Source Offset (GP_SRC_OFFSET)2596.4.2.3 Vector Error (GP_VEC_ERR)2606.4.2.4 Stride (GP_STRIDE)2606.4.2.5 BLT Width/Height (GP_WID_HEIGHT)2616.4.2.6 Vector Length (GP_VEC_LEN)2616.4.2.7 Source Color Foreground (GP_SRC_COLOR_FG)2626.4.2.8 Source Color Background (GP_SRC_COLOR_BG)2636.4.2.9 Pattern Color (GP_PAT_COLOR_x)2646.4.2.10 Pattern Data (GP_PAT_DATA_x)2656.4.2.11 Raster Mode (GP_RASTER_MODE)2656.4.2.12 Vector Mode (GP_VECTOR_MODE)2676.4.2.13 BLT Mode (GP_BLT_MODE)2686.4.2.14 Status and Reset (GP_BLT_STATUS, GP_RESET)2696.4.2.15 Host Source (GP_HST_SRC)2696.4.2.16 Base Offset (GP_BASE_OFFSET)2706.4.2.17 Command Top (GP_CMD_TOP)2706.4.2.18 Command Bottom (GP_CMD_BOT)2716.4.2.19 Command Read (GP_CMD_READ)2716.4.2.20 Command Write (GP_CMD_WRITE)2726.4.2.21 Offset (GP_CH3_OFFSET)2726.4.2.22 Stride (GP_CH3_MODE_STR)2736.4.2.23 Width/Height (GP_CH3_WIDHI)2756.4.2.24 Host Source (GP_CH3_HSRC)2756.4.2.25 LUT Index (GP_LUT_INDEX)2766.4.2.26 LUT Data (GP_LUT_DATA)2766.4.2.27 Interrupt Control (GP_INT_CNTRL)2776.5 Display Controller2786.5.1 GUI Functional Overview2816.5.1.1 Display Mode Support2816.5.1.2 Display FIFO2836.5.1.3 Hardware Cursor and Icon Overlays2836.5.1.4 Display Refresh Compression2856.5.1.5 Dirty/Valid RAM2856.5.1.6 Palette/Gamma RAM2856.5.1.7 Display Address Generator2856.5.1.8 Display Timing Generator2856.5.1.9 Video Overlay Support2866.5.1.10 Output Formats2876.5.2 VBI Data2876.5.3 GenLock2876.5.4 VGA Block Functional Overview2886.5.4.1 VGA Modes2886.5.5.2 Graphics Controller2896.5.5.3 Write Modes2906.5.5.4 Read Modes2916.5.6 Graphics Scaler/Filter2936.5.7 Color Key Elimination2966.5.8 Using the Graphics Filter2966.5.9 Interlaced Modes2976.5.10 Interlaced Timing Examples2986.6 Display Controller Register Descriptions3006.6.1 Standard GeodeLink™ Device (GLD) Registers (MSRs)3056.6.1.1 GLD Capabilities MSR (GLD_MSR_CAP)3056.6.1.2 GLD Master Configuration MSR (GLD_MSR_CONFIG)3056.6.1.3 GLIU0 Device SMI MSR (GLD_MSR_SMI)3066.6.1.4 GLD Error MSR (GLD_MSR_ERROR)3086.6.1.5 GLD Power Management MSR (GLD_MSR_PM)3106.6.1.6 GLIU0 Device Diagnostic MSR (GLD_MSR_DIAG)3106.6.2 Display Controller Specific MSRs3116.6.2.1 SPARE MSR3116.6.2.2 DC RAM Control MSR (DC_RAM_CTL_MSR)3116.6.3 Configuration and Status Registers3126.6.3.1 DC Unlock (DC_UNLOCK)3126.6.3.2 DC General Configuration (DC_GENERAL_CFG)3146.6.3.3 DC Display Configuration (DC_DISPLAY_CFG)3176.6.3.4 DC Arbitration Configuration (DC_ARB_CFG)3196.6.4 Memory Organization Registers3216.6.4.1 DC Frame Buffer Start Address (DC_FB_ST_OFFSET)3216.6.4.2 DC Compression Buffer Start Address (DC_CB_ST_OFFSET)3226.6.4.3 DC Cursor Buffer Start Address (DC_CURS_ST_OFFSET)3226.6.4.4 DC Video Y Buffer Start Address Offset (DC_VID_Y_ST_OFFSET)3236.6.4.5 DC Video U Buffer Start Address Offset (DC_VID_U_ST_OFFSET)3236.6.4.6 DC Video V Buffer Start Address Offset (DC_VID_V_ST_OFFSET)3246.6.4.7 DC Dirty/Valid Region Top (DC_DV_TOP)3246.6.4.8 DC Line Size (DC_LINE_SIZE)3256.6.4.9 DC Graphics Pitch (DC_GFX_PITCH)3266.6.4.10 DC Video YUV Pitch (DC_VID_YUV_PITCH)3266.6.5 Timing Registers3276.6.5.1 DC Horizontal and Total Timing (DC_H_ACTIVE_TIMING)3286.6.5.2 DC CRT Horizontal Blanking Timing (DC_H_BLANK_TIMING)3296.6.5.3 DC CRT Horizontal Sync Timing (DC_H_SYNC_TIMING)3296.6.5.4 DC Vertical and Total Timing (DC_V_ACTIVE_TIMING)3306.6.5.5 DC CRT Vertical Blank Timing (DC_V_BLANK_TIMING)3316.6.5.6 DC CRT Vertical Sync Timing (DC_V_SYNC_TIMING)3316.6.5.7 DC Frame Buffer Active Region Register (DC_FB_ACTIVE)3326.6.6 Cursor Position and Line Count/Status Registers3326.6.6.1 DC Cursor X Position (DC_CURSOR_X)3326.6.6.2 DC Cursor Y Position (DC_CURSOR_Y)3336.6.6.3 DC Line Count/Status (DC_LINE_CNT/STATUS)3336.6.7 Palette Access FIFO Diagnostic Registers3356.6.7.1 DC Palette Address (DC_PAL_ADDRESS)3356.6.7.2 DC Palette Data (DC_PAL_DATA)3366.6.7.3 DC Display FIFO Diagnostic (DC_DFIFO_DIAG)3366.6.7.4 DC Compression FIFO Diagnostic (DC_CFIFO_DIAG)3376.6.8 Video Downscaling3386.6.8.1 DC Video Downscaling Delta (DC_VID_DS_DELTA)3386.6.9 GLIU Control Registers3396.6.9.1 DC GLIU0 Memory Offset (DC_GLIU0_MEM_OFFSET)3396.6.9.2 DC Dirty/Valid RAM Control (DC_DV_CTL)3396.6.9.3 DC Dirty/Valid RAM Access (DC_DV_ACCESS)3406.6.10 Graphics Scaling Control Registers3416.6.10.1 DC Graphics Filter Scale (DC_GFX_SCALE)3416.6.10.2 DC IRQ/Filter Control (DC_IRQ_FILT_CTL)3426.6.10.3 DC Filter Coefficient Data Register 1 (DC_FILT_COEFF1)3436.6.10.4 DC Filter Coefficient Data Register 2 (DC_FILT_COEFF2)3446.6.11 VBI Control Registers3446.6.11.1 DC VBI Even Control (DC_VBI_EVEN_CTL)3446.6.11.2 DC VBI Odd Control (DC_VBI_ODD_CTL)3456.6.11.3 DC VBI Horizontal Control (DC_VBI_HOR)3456.6.11.4 DC VBI Odd Line Enable (DC_VBI_LN_ODD)3466.6.11.5 DC VBI Even Line Enable (DC_VBI_LN_EVEN)3466.6.11.6 DC VBI Pitch and Size (DC_VBI_PITCH)3476.6.12 Color Key Control Registers3476.6.12.1 DC Color Key (DC_CLR_KEY)3476.6.12.2 DC Color Key Mask (DC_CLR_KEY_MASK)3486.6.12.3 DC Color Key Horizontal Position (DC_CLR_KEY_X)3486.6.12.4 DC Color Key Vertical Position (DC_CLR_KEY_Y)3486.6.12.5 DC Interrupt (DC_IRQ)3496.6.13 Interrupt and GenLock Registers3506.6.13.1 DC GenLock Control (DC_GENLK_CTL)3506.6.14 Even Field Video Address Registers3516.6.14.1 DC Even Field Video Y Start Address Offset (DC_VID_EVEN_Y_ST_OFFSET)3516.6.14.2 DC Even Field Video U Start Address Offset (DC_VID_EVEN_U_ST_OFFSET)3526.6.14.3 DC Even Field Video V Start Address Offset (DC_VID_EVEN_V_ST_OFFSET)3526.6.15 Even Field Vertical Timing Registers3536.6.15.1 DC Vertical and Total Timing for Even Fields (DC_V_ACTIVE_EVEN_TIMING)3536.6.15.2 DC CRT Vertical Blank Timing for Even Fields (DC_V_BLANK_EVEN_TIMING)3546.6.15.3 DC CRT Vertical Sync Timing for Even Fields (DC_V_SYNC_EVEN_TIMING)3546.6.16 VGA Block Configuration Registers3556.6.16.1 VGA Configuration (VGA_CONFIG)3556.6.16.2 VGA Status (VGA_STATUS)3556.6.17 VGA Block Standard Registers3566.6.17.1 VGA Miscellaneous Output3566.6.17.2 VGA Input Status Register 03576.6.17.3 VGA Input Status Register 13576.6.17.4 VGA Feature Control3576.6.18 VGA Sequencer Registers3586.6.18.1 VGA Sequencer Index3586.6.18.2 VGA Sequencer Data3586.6.18.3 VGA Reset3586.6.18.4 VGA Clocking Mode3596.6.18.5 VGA Map Mask3596.6.18.6 VGA Character Map Select3606.6.18.7 VGA Memory Mode3606.6.19 VGA CRT Controller Registers3616.6.19.1 CRTC Index3626.6.19.2 CRTC Data3636.6.19.3 Horizontal Total3636.6.19.4 Horizontal Display Enable End3636.6.19.5 Horizontal Blank Start3636.6.19.6 Horizontal Blank End3646.6.19.7 Horizontal Sync Start3646.6.19.8 Horizontal Sync End3646.6.19.9 Vertical Total3656.6.19.10 Overflow3656.6.19.11 Preset Row Scan3656.6.19.12 Maximum Scan Line3666.6.19.13 Cursor Start3666.6.19.14 Cursor End3676.6.19.15 Start Address High3676.6.19.16 Start Address Low3676.6.19.17 Cursor Location High3676.6.19.18 Cursor Location Low3686.6.19.19 Vertical Sync Start3686.6.19.20 Vertical Sync End3686.6.19.21 Vertical Display Enable End3696.6.19.22 Offset3696.6.19.23 Underline Location3696.6.19.24 Vertical Blank Start3706.6.19.25 Vertical Blank End3706.6.19.26 CRTC Mode Control3706.6.19.27 Line Compare3726.6.19.28 CPU Data Latch State3726.6.19.29 Attribute Index/Data FF State3726.6.19.30 Attribute Index State3736.6.20 VGA Graphics Controller Registers3736.6.20.1 VGA Graphics Controller Index3736.6.20.2 VGA Graphics Controller Data3746.6.20.3 VGA Set/Reset3746.6.20.4 VGA Enable Set/Reset3746.6.20.5 VGA Color Compare3756.6.20.6 VGA Data Rotate3756.6.20.7 VGA Read Map Select3766.6.20.8 VGA Graphics Mode3766.6.20.9 VGA Miscellaneous3776.6.20.10 VGA Color Don’t Care3786.6.20.11 VGA Bit Mask3786.6.21 Attribute Controller Registers3786.6.21.1 Attribute Controller Index/Data3796.6.21.2 EGA Palette3796.6.21.3 Attribute Mode Control3806.6.21.4 Overscan Color3806.6.21.5 Color Plane Enable3816.6.21.6 Horizontal Pel Panning3816.6.21.7 Color Select3826.6.22 Video DAC Registers3826.6.22.1 Video DAC Palette Address3836.6.22.2 Video DAC State3836.6.22.3 Video DAC Palette Data3836.6.22.4 Video DAC Palette Mask3846.6.23 VGA Block Extended Registers3846.6.23.1 ExtendedRegisterLock3856.6.23.2 ExtendedModeControl3856.6.23.3 ExtendedStartAddress3856.6.23.4 WriteMemoryAperture3866.6.23.5 ReadMemoryAperture3866.6.23.6 BlinkCounterCtl3866.6.23.7 BlinkCounter3876.6.23.8 VGALatchSavRes3876.6.23.9 DACIFSavRes3876.7 Video Processor3886.7.1 Architecture Overview3886.7.2 Functional Description3906.7.2.1 Video Formatter3916.7.2.2 4x4 Filter/Scaler3916.7.2.3 Horizontal Downscaling3926.7.3 X and Y Upscaler3936.7.4 Color Space Converter3936.7.5 Video Overlay3946.7.5.1 Alpha-Blending3946.7.5.2 Gamma RAM3976.7.5.3 Video Processor Module Display Interface3976.7.5.4 Video Interface3976.7.6 Video Output Port3986.7.6.1 Functional Overview3986.7.6.2 Supported Features3986.7.6.3 HBLANK and VBLANK Signals3996.7.6.4 Interface to Video Processor4016.7.6.5 Operating Modes4026.7.6.6 New VIP 2.0 Video Flags4046.7.6.7 BT.601 Support4046.7.6.8 VIP 2.0 Level System4046.7.6.9 VBI Data4046.7.7 Flat Panel Display Controller4056.7.7.1 FP Functional Overview4056.7.7.2 FP Architecture Overview4056.7.7.3 FP Functional Description4066.7.8 VP Resolution Table4116.7.9 Display RGB Modes4116.8 Video Processor Register Descriptions4126.8.1 Standard GeodeLink™ Device MSRs4156.8.1.1 GLD Capabilities MSR (GLD_MSR_CAP)4156.8.1.2 GLD Master Configuration MSR (GLD_MSR_CONFIG)4156.8.1.3 GLD SMI MSR (GLD_MSR_SMI)4176.8.1.4 GLD Error MSR (GLD_MSR_ERROR)4176.8.1.5 GLD Power Management MSR (GLD_MSR_PM)4186.8.1.6 GLD Diagnostic MSR (GLD_MSR_DIAG)4186.8.2 Video Processor Module Specific MSRs4196.8.2.1 VP Diagnostic MSR (MSR_DIAG_VP)4196.8.2.2 Pad Select MSR (MSR_PADSEL)4206.8.3 Video Processor Module Control/Configuration Registers4216.8.3.1 Video Configuration (VCFG)4216.8.3.2 Display Configuration (DCFG)4226.8.3.3 Video X Position (VX)4246.8.3.4 Video Y Position (VY)4256.8.3.5 Video Scale (SCL)4256.8.3.6 Video Color Key Register (VCK)4266.8.3.7 Video Color Mask (VCM)4276.8.3.8 Palette Address (PAR)4286.8.3.9 Palette Data (PDR)4286.8.3.10 Saturation Scale (SLR)4296.8.3.11 Miscellaneous (MISC)4306.8.3.12 CRT Clock Select (CCS)4316.8.3.13 Video Y Scale (VYS)4316.8.3.14 Video X Scale (VXS)4316.8.3.15 Video Downscaler Control (VDC)4326.8.3.16 CRC Signature (CRC)4336.8.3.17 32-Bit CRC Signature (CRC32)4346.8.3.18 Video De-Interlacing and Alpha Control (VDE)4346.8.3.19 Cursor Color Key (CCK)4366.8.3.20 Cursor Color Mask (CCM)4376.8.3.21 Cursor Color 1 (CC1)4376.8.3.22 Cursor Color 2 (CC2)4386.8.3.23 Alpha Window 1 X Position (A1X)4386.8.3.24 Alpha Window 1 Y Position (A1Y)4396.8.3.25 Alpha Window 1 Color (A1C)4396.8.3.26 Alpha Window 1 Control (A1T)4406.8.3.27 Alpha Window 2 X Position (A2X)4416.8.3.28 Alpha Window 2 Y Position (A2Y)4426.8.3.29 Alpha Window 2 Color (AC2)4426.8.3.30 Alpha Window 2 Control (A2T)4436.8.3.31 Alpha Window 3 X Position (A3X)4446.8.3.32 Alpha Window 3 Y Position (A3Y)4456.8.3.33 Alpha Window 3 Color (A3C)4456.8.3.34 Alpha Window 3 Control (A3T)4466.8.3.35 Video Request (VRR)4476.8.3.36 Alpha Watch (AWT)4486.8.3.37 Video Processor Test Mode (VTM)4486.8.3.38 Even Video Y Position (VYE)4496.8.3.39 Even Alpha Window 1 Y Position (A1YE)4496.8.3.40 Even Alpha Window 2 Y Position (A2YE)4506.8.3.41 Even Alpha Window 3 Y Position (A3YE)4506.8.3.42 Video Coefficient RAM (VCR)4516.8.3.43 Panel Timing Register 1 (PT1)4516.8.3.44 Panel Timing Register 2 (PT2)4536.8.3.45 Power Management (PM)4546.8.3.46 Dither and Frame Rate Control (DFC)4566.8.3.47 Dither RAM Control and Address (DCA)4576.8.3.48 Dither Memory Data (DMD)4586.8.3.49 Panel CRC Signature (CRC)4586.8.3.50 32-Bit Panel CRC (CRC32)4596.8.3.51 Video Output Port Configuration (VOP_CONFIG)4596.8.3.52 Video Output Port Signature (VOP_SIG)4616.9 Video Input Port4626.9.1 Features4626.9.1.1 Performance Metrics4626.9.2 VIP Block Descriptions4636.9.2.1 Input Formatter4646.9.2.2 Input Control4646.9.2.3 VIP Capture RAM4646.9.2.4 VIP Register Block4646.9.2.5 GLIU Interface4646.9.3 Functional Description4656.9.4 VIP Operation Modes4656.9.5 Mode 1a,b,c - VIP Input Data (simplified BT.656)4666.9.5.1 SAV/EAV Packets4666.9.5.2 Ancillary Packets4696.9.6 Message Passing Mode4706.9.7 Data Streaming Mode4706.9.8 BT.601 Mode4716.9.9 YUV 4:2:2 to YUV 4:2:0 Translation4736.9.10 Software Model4756.9.10.1 Video Data Buffers4766.9.10.2 VBI Data Buffers4766.9.10.3 Ancillary Data Buffers4766.9.10.4 Message Passing/Data Streaming Modes4766.9.11 Bob and Weave4806.9.11.1 Bob4806.9.11.2 Weave4806.9.12 VIP Interrupts4806.9.13 VIP Input Video Status4816.10 Video Input Port Register Descriptions4826.10.1 Standard GeodeLink™ Device (GLD) MSRs4846.10.1.1 GLD Capabilities MSR (GLD_MSR_CAP)4846.10.1.2 GLD Configuration MSR (GLD_MSR_CONFIG)4846.10.1.3 GLD SMI MSR (GLD_MSR_SMI)4856.10.1.4 GLD Error MSR (GLD_MSR_ERROR)4866.10.1.5 GLD Power Management Register (GLD_MSR_PM)4876.10.1.6 GLD Diagnostic MSR (GLD_MSR_DIAG)4876.10.2 VIP Control/Configuration Registers4886.10.2.1 VIP Control Register 1 (VIP_CTL_REG1)4886.10.2.2 VIP Control Register 2 (VIP_CTL_REG2)4906.10.2.3 VIP Status (VIP_STATUS)4926.10.2.4 VIP Interrupt (VIP_INT)4946.10.2.5 VIP Current/Target (VIP_CUR_TAR)4956.10.2.6 VIP Max Address (VIP_MAX_ADDR)4956.10.2.7 VIP Task A Video Even Base Address (VIP_TASK_A_VID_EVEN_BASE)4966.10.2.8 VIP Task A Video Odd Base Address (VIP_TASK_A_VID_ODD_BASE)4966.10.2.9 VIP Task A VBI Even Base Address (VIP_TASK_A_VBI_EVEN_BASE)4976.10.2.10 VIP Task A VBI Odd Base Address (VIP_TASK_A_VBI_ODD_BASE)4976.10.2.11 VIP Task A Video Pitch (VIP_TASK_A_VID_PITCH)4986.10.2.12 VIP Control Register 3 (VIP_CONTRL_REG3)4986.10.2.13 VIP Task A V Offset (VIP_TASK_A_V_OFFSET)4996.10.2.14 VIP Task A U Offset (VIP_TASK_A_U_OFFSET)5006.10.2.15 VIP Task B Video Even Base/Horizontal End (VIP_TASK_B_VID_EVEN_BASE_HORIZ_END)5006.10.2.16 VIP Task B Video Odd Base/Horizontal Start (VIP_TASK_B_VID_ODD_BASE_HORIZ_START)5016.10.2.17 VIP Task B VBI Even Base/VBI End (VIP_TASK_B_VBI_EVEN_BASE_VBI_END)5016.10.2.18 VIP Task B VBI Odd Base/VBI Start (VIP_TASK_B_VBI_ODD_BASE_VBI_START)5026.10.2.19 VIP Task B Data Pitch/Vertical Start Even (VIP_TASK_B_DATA_PITCH_VERT_START_EVEN)5026.10.2.20 VIP Task B V Offset (VIP_TASK_B_V_Offset)5036.10.2.21 VIP Task B U Offset (VIP_TASK_B_U_OFFSET)5046.10.2.22 VIP Ancillary Data/Message Passing/Data Streaming Buffer1 Base Address (VIP_ANC_MSG_1_BASE)5046.10.2.23 VIP Ancillary Data/Message Passing/Data Streaming Buffer 2 Base Address (VIP_ANC_MSG_2_BASE)5056.10.2.24 VIP Ancillary Data/Message Passing/Data Streaming Buffer Size (VIP_ANC_MSG_SIZE)5056.10.2.25 VIP Page Offset/ Page Count (VIP_PAGE_OFFSET)5066.10.2.26 VIP Vertical Start/Stop (VIP_VERT_START_STOP)5066.10.2.27 VIP FIFO Address (VIP_FIFO_R_W_ADDR)5076.10.2.28 VIP FIFO Data (VIP_FIFO_DATA)5076.10.2.29 VIP VSYNC Error Count (VIP_SYNC_ERR_COUNT)5086.10.2.30 VIP Task A U Even Offset (VIP_TASK_A_U_EVEN_OFFSET)5086.10.2.31 VIP Task A V Even Offset (VIP_TASK_A_V_EVEN_OFFSET)5096.11 Security Block5106.11.1 Security Block Features5106.11.1.1 Performance Metrics5106.11.2 Functional Description5116.11.2.1 EEPROM ID Interface5126.11.2.2 Security Block Interrupts5126.11.2.3 GLIU Interface5126.12 Security Block Register Descriptions5136.12.1 Standard GeodeLink™ (GLD) Device MSRs5156.12.1.1 GLD Capabilities MSR (GLD_MSR_CAP)5156.12.1.2 GLD Master Configuration MSR (GLD_MSR_CONFIG)5156.12.1.3 GLD SMI MSR (GLD_MSR_SMI)5166.12.1.4 GLD Error MSR (GLD_MSR_ERROR)5166.12.1.5 GLD Power Management MSR (GLD_MSR_PM)5186.12.1.6 GLD Diagnostic MSR (GLD_MSR_DIAG)5186.12.2 Security Block Specific MSRs5196.12.2.1 GLD Control MSR (GLD_MSR_CTRL)5196.12.3 Security Block Configuration/Control Registers5206.12.3.1 SB Control A (SB_CTL_A)5206.12.3.2 SB Control B (SB_CTL_B)5216.12.3.3 SB AES Interrupt (SB_AES_INT)5226.12.3.4 SB Source A (SB_SOURCE_A)5226.12.3.5 SB Destination A (SB_DEST_A)5236.12.3.6 SB Length A (SB_LENGTH_A)5236.12.3.7 SB Source B (SB_SOURCE_B)5246.12.3.8 SB Destination B (SB_DEST_B)5246.12.3.9 SB Length B (SB_LENGTH_B)5256.12.3.10 SB Writable Key 0 (SB_WKEY_0)5256.12.3.11 SB Writable Key 1 (SB_WKEY_1)5266.12.3.12 SB Writable Key 2 (SB_WKEY_2)5266.12.3.13 SB Writable Key 3 (SB_WKEY_3)5276.12.3.14 SB CBC Initialization Vector 0 (SB_CBC_IV_0)5276.12.3.15 SB CBC Initialization Vector 1 (SB_CBC_IV_1)5286.12.3.16 SB CBC Initialization Vector 2 (SB_CBC_IV_2)5286.12.3.17 SB CBC Initialization Vector 3 (SB_CBC_IV_3)5286.12.3.18 SB Random Number (SB_RANDOM_NUM)5296.12.3.19 SB Random Number Status (SB_RANDOM_NUM_STATUS)5296.12.3.20 SB EEPROM Command (SB_EEPROM_COMM)5306.12.3.21 SB EEPROM Address (SB_EEPROM_ADDR)5316.12.3.22 SB EEPROM Data (SB_EEPROM_DATA)5316.12.3.23 SB EEPROM Security State (SB_EEPROM_SEC_STATE)5326.13 GeodeLink™ Control Processor5336.13.1 TAP Controller5336.13.2 Reset Logic5356.13.3 Clock Control5356.13.3.1 Power Management5356.13.4 Companion Device Interface5366.13.4.1 GIO_GLIU5366.13.4.2 GIO_SYNC5366.13.4.3 GIO_PCI5366.14 GeodeLink™ Control Processor Register Descriptions5396.14.1 Standard GeodeLink™ Device MSRs5416.14.1.1 GLD Capabilities MSR (GLD_MSR_CAP)5416.14.1.2 GLD Master Configuration MSR (GLD_MSR_CONFIG)5416.14.1.3 GLD SMI MSR (GLD_MSR_SMI)5426.14.1.4 GLD Error MSR (GLD_MSR_ERROR)5436.14.1.5 GLD Power Management MSR (GLD_MSR_PM)5446.14.1.6 GLD Diagnostic MSR (GLD_MSR_DIAG)5446.14.2 GLCP Specific MSRs - GLCP Control MSRs5456.14.2.1 GLCP Clock Disable Delay Value (GLCP_CLK_DIS_DELAY)5456.14.2.2 GLCP Clock Mask for Sleep Request (GLCP_PMCLKDISABLE)5456.14.2.3 Chip Fabrication Information (GLCP_FAB)5476.14.2.4 GLCP Global Power Management Controls (GLCP_GLB_PM)5476.14.2.5 GLCP Debug Output from Chip (GLCP_DBGOUT)5486.14.2.6 GLCP Processor Status (GLCP_PROCSTAT)5486.14.2.7 GLCP DOWSER (GLCP_DOWSER)5496.14.2.8 GLCP I/O Delay Controls (GLCP_DELAY_CONTROLS)5496.14.2.9 GLCP Clock Control (GLCP_CLKOFF)5516.14.2.10 GLCP Clock Active (GLCP_CLKACTIVE)5526.14.2.11 GLCP Clock Mask for Debug Clock Stop Action (GLCP_CLKDISABLE)5536.14.2.12 GLCP Clock Active Mask for Suspend Acknowledge (GLCP_CLK4ACK)5536.14.2.13 GLCP System Reset and PLL Control (GLCP_SYS_RSTPLL)5546.14.2.14 GLCP Dot Clock PLL Control (GLCP_DOTPLL)5576.14.2.15 GLCP Debug Clock Control (GLCP_DBGCLKCTL)5596.14.2.16 Chip Revision ID (GLCP_CHIP_REVID)5596.14.2.17 GLCP Control (GLCP_CNT)5606.14.2.18 GLCP Level 2 (GLCP_LVL2)5606.14.2.19 GLCP Throttle or C2 Start Delay (GLCP_TH_SD)5616.14.2.20 GLCP Scale Factor (GLCP_TH_SF)5616.14.2.21 GLCP Processor Throttle Off Delay (GLCP_TH_OD)5626.14.3 GLCP IGNNE I/Os5626.14.4 GLCP Specific MSRs - GLCP Debug Interface MSRs5636.14.4.1 GLCP DAC (GLCP_DAC)5636.14.5 GLCP Specific MSRs - GLCP Companion Device Interface MSRs5646.14.5.1 CPU A20M Signal (MSR_A20M)5646.14.5.2 CPU INIT Signal (MSR_INIT)5646.14.5.3 GLIU Device Interrupt Status (MSR_INTAX)5656.15 GeodeLink™ PCI Bridge5666.15.1 GeodeLink™ Interface Block5676.15.2 FIFO/Synchronization Block5676.15.3 Transaction Forwarding Block5676.15.3.1 Atomic External MSR Access5676.15.4 PCI Bus Interface Block5696.15.4.1 PCI Configuration and Virtual PCI Header Support5696.15.5 PCI Arbiter5706.15.6 Exception Handling5716.15.6.1 Out-Bound Write Exceptions5716.15.6.2 Out-Bound Read Exceptions5716.15.6.3 In-Bound Write Exceptions5716.15.6.4 In-Bound Read Exceptions5716.16 GeodeLink™ PCI Bridge Register Descriptions5726.16.1 Standard GeodeLink™ Device (GLD) MSRs5746.16.1.1 GLD Capabilities MSR (GLD_MSR_CAP)5746.16.1.2 GLD Master Configuration MSR (GLD_MSR_CONFIG)5746.16.1.3 GLD SMI MSR (GLD_MSR_SMI)5756.16.1.4 GLD Error MSR (GLD_MSR_ERROR)5766.16.1.5 GLD Power Management MSR (GLD_MSR_PM)5776.16.1.6 GLD Diagnostic MSR (GLD_MSR_DIAG)5776.16.2 GLPCI Specific Registers5786.16.2.1 GLPCI Global Control (GLPCI_CTRL)5786.16.2.2 GLPCI Arbiter Control (GLPCI_ARB)5816.16.2.3 GLPCI VPH / PCI Configuration Cycle Control (GLPCI_PBUS)5846.16.2.4 GLPCI Debug Packet Configuration (GLPCI_DEBUG)5846.16.2.5 GLPCI Fixed Region Enables (GLPCI_REN)5846.16.2.6 GLPCI Fixed Region Configuration A0-BF (GLPCI_A0)5856.16.2.7 GLPCI Fixed Region Configuration C0-DF (GLPCI_C0)5866.16.2.8 GLPCI Fixed Region Configuration E0-FF (GLPCI_E0)5876.16.2.9 GLPCI Memory Region 0 Configuration (GLPCI_R0)5886.16.2.10 GLPCI Memory Region 1 Configuration (GLPCI_R1)5896.16.2.11 GLPCI Memory Region 2 Configuration (GLPCI_R2)5906.16.2.12 GLCPI Memory Region 3 Configuration (GLPCI_R3)5916.16.2.13 GLCPI Memory Region 4 Configuration (GLPCI_R4)5926.16.2.14 GLPCI Memory Region 5 Configuration (GLPCI_R5)5936.16.2.15 GLPCI External MSR Access Configuration (GLPCI EXT_MSR)5946.16.2.16 GLPCI Spare5956.16.2.17 GLPCI General Purpose I/O (GLPCI_GPIO)596Electrical Specifications5977.1 Electrical Connections5977.1.1 PWR/GND Connections and Decoupling5977.1.2 NC-Designated Balls5977.1.3 Unused Inputs5977.2 Absolute Maximum Ratings5977.3 Operating Conditions5987.4 DC Current5997.4.1 Power State Parameter Definitions5997.4.2 Definition and Measurement Techniques of Current Parameters5997.4.3 DC Current Measurements5997.5 DC Characteristics6047.6 AC Characteristics607Instruction Set6198.1 General Instruction Set Format6198.1.1 Prefix (Optional)6208.1.2 Opcode6218.1.2.1 w Field (Operand Size)6218.1.2.2 d Field (Operand Direction)6218.1.2.3 s Field (Immediate Data Field Size)6218.1.2.4 eee Field (MOV-Instruction Register Selection)6228.1.3 mod and r/m Byte (Memory Addressing)6228.1.4 reg Field6248.1.4.1 sreg2 Field (ES, CS, SS, DS Register Selection)6248.1.4.2 sreg3 Field (FS and GS Segment Register Selection)6248.1.5 s-i-b Byte (Scale, Indexing, Base)6258.1.5.1 ss Field (Scale Selection)6258.1.5.2 Index Field (Index Selection)6258.1.5.3 Base Field (s-i-b Present)6268.2 CPUID Instruction Set6278.2.1 Standard CPUID Levels6278.2.1.1 CPUID Instruction with EAX = 00000000h6278.2.1.2 CPUID Instruction with EAX = 00000001h6278.2.2 Extended CPUID Levels6298.2.2.1 CPUID Instruction with EAX = 80000000h6298.2.2.2 CPUID Instruction with EAX = 80000001h6298.2.2.3 CPUID Instruction with EAX = 80000002h, 80000003h, or 80000004h6318.2.2.4 CPUID Instruction with EAX = 80000005h6328.2.2.5 CPUID Instruction with EAX = 80000006h6328.3 Processor Core Instruction Set6338.3.1 Opcodes6338.3.2 Clock Counts6338.3.3 Flags6338.3.4 Non-Standard Processor Core Instructions6468.3.4.1 DMINT - Enter Debug Management Mode6468.3.4.2 ICEBP - Call Debug Exception Handler6478.3.4.3 MOV - Move to/from Test Registers6488.3.4.4 RDM - Leave Debug Management Mode6498.3.4.5 RSDC - Restore Segment Register and Descriptor6508.3.4.6 RSLDT - Restore Local Descriptor Table Register and Descriptor6518.3.4.7 RSM - Leave System Management Mode6528.3.4.8 RSTS - Restore Task Register and Descriptor6538.3.4.9 SETALC - Set AL to CF6538.3.4.10 SMINT - Enter System Management Mode6548.3.4.11 Exceptions6558.3.4.12 SVDC - Save Segment Register and Descriptor6568.3.4.13 SVLDT - Save Local Descriptor Table Register and Descriptor6568.3.4.14 SVTS - Save Task Register and Descriptor6578.4 MMX™, FPU, and AMD 3DNow!™ Technology Instructions Sets6588.4.1 Non-Standard AMD 3DNow!™ Technology Instructions6748.4.1.1 PFRCPV - Floating-Point Reciprocal Approximation6748.4.1.2 PFRSQRTV - Floating-Point Reciprocal Square Root Approximation674Package Specifications6759.1 Physical Dimensions675Support Documentation677A.1 Order Information677A.2 Data Book Revision History679サイズ: 5.51MBページ数: 680Language: Englishマニュアルを開く