Analog Devices AD9102 Evaluation Board AD9102-EBZ マニュアル

目次

• Features

  1
• Applications

  1
• General Description

  1
• Product Highlights

  1
• Functional Block Diagram

  1
• Revision History

  2
• Specifications

  3
  • DC Specifications (3.3 V)

    3
  • DC Specifications (1.8 V)

    4
  • Digital Timing Specifications (3.3 V)

    4
  • Digital Timing Specifications (1.8 V)

    5
  • Input/Output Signal Specifications

    5
  • AC Specifications (3.3 V)

    6
  • AC Specifications (1.8 V)

    6
  • Power Supply Voltage Inputs and Power Dissipation

    7
• Absolute Maximum Ratings

  8
  • Thermal Resistance

    8
  • ESD Caution

    8
• Pin Configuration and Function Descriptions

  9
• Typical Performance Characteristics

  11
• Terminology

  16
• Theory of Operation

  17
  • SPI Port

    18
    • Writing to On-Chip SRAM

      18
    • Double SPI for Write for SRAM

      18
    • Configuration Register Update Procedure

      18
  • DAC Transfer Function

    19
  • Analog Current Outputs

    19
  • Setting IOUTFS, DAC Gain

    19
    • Voltage Reference

      19
    • Programming Internal VREFIO

      19
    • RSET Resistors

      19
  • Automatic IOUTFS Calibration

    19
  • Clock Input

    20
  • DAC Output Clock Edge

    21
  • Generating Signal Patterns

    21
    • RUN Bit

      21
    • Pin

      21
    • PATTERN Bit (Read Only)

      21
    • Pattern Types

      21
  • Pattern Generator Programming

    21
    • Setting Pattern Period

      21
    • Setting Waveform Start Delay Base

      21
  • DAC Input Datapaths

    22
    • DAC Digital Gain Multiplier

      22
    • DAC Digital Offset Summer

      22
    • DAC Waveform Selectors

      22
    • Pattern Period Repeat Controller

      22
    • Number of DDS Cycles

      22
    • DDS Phase Shift

      22
  • DOUT Function

    22
    • Manually Controlled DOUT

      22
    • Pattern Generator Controlled DOUT

      22
  • Direct Digital Synthesizer (DDS)

    23
  • SRAM

    23
    • Incrementing Pattern Generation Mode SRAM Address Counters

      23
  • Sawtooth Generator

    23
  • Pseudorandom Signal Generator

    24
  • DC Constant

    24
  • Power Supply Notes

    24
  • Power Down Capabilities

    24
• Applications

  25
  • Signal Generation Examples

    25
• Register Map

  26
• Register Descriptions

  28
  • SPI Control Register (SPICONFIG, Address 0x00)

    28
  • Power Status Register (POWERCONFIG, Address 0x01)

    28
  • Clock Control Register (CLOCKCONFIG, Address 0x02)

    29
  • Reference Resistor Register (REFADJ, Address 0x03)

    29
  • DAC Analog Gain Register (DACAGAIN, Address 0x07)

    29
  • DAC Analog Gain Range Register (DACRANGE, Address 0x08)

    29
  • FSADJ Register (DACRSET, Address 0x0C)

    30
  • Calibration Register (CALCONFIG, Address 0x0D)

    30
  • Comp Offset Register (COMPOFFSET, Address 0x0E)

    30
  • Update Pattern Register (RAMUPDATE, Address 0x1D)

    30
  • Command/Status Register (PAT_STATUS, Address 0x1E)

    31
  • Command/Status Register (PAT_TYPE, Address 0x1F)

    31
  • Trigger Start to Real Pattern Delay Register (PATTERN_DLY, Address 0x20)

    31
  • DAC Digital Offset Register (DACDOF, Address 0x25)

    31
  • Wave Select Register (WAV_CONFIG, Address 0x27)

    31
  • DAC Time Control Register (PAT_TIMEBASE, Address 0x28)

    32
  • Pattern Period Register (PAT_PERIOD, Address 0x29)

    32
  • DAC Pattern Repeat Cycles Register (DAC_PAT, Address 0x2B)

    32
  • Start to DOUT Signal Register (DOUT_START, Address 0x2C)

    32
  • DOUT CONFIG Register (DOUT_CONFIG, Address 0x2D)

    32
  • DAC Constant Value Register (DAC_CST, Address 0x31)

    32
  • DAC Digital Gain Register (DAC_DGAIN, Address 0x35)

    33
  • DAC Sawtooth Config Register (SAW_CONFIG, Address 0x37)

    33
  • DDS Tuning Word MSB Register (DDS_TW32, Address 0x3E)

    33
  • DDS Tuning Word LSB Register (DDS_TW1, Address 0x3F)

    33
  • DDS Phase Offset Register (DDS_PW, Address 0x43)

    33
  • Pattern Control 1 Register (TRIG_TW_SEL, Address 0x44)

    33
  • Pattern Control 2 Register (DDS_CONFIG, Address 0x45)

    34
  • TW_RAM_CONFIG Register (TW_RAM_CONFIG, Address 0x47)

    34
  • Start Delay Register (START_DLY, Address 0x5C)

    34
  • Start Address Register (START_ADDR, Address 0x5D)

    34
  • Stop Address Register (STOP_ADDR, Address 0x5E)

    35
  • DDS Cycles Register (DDS_ CYC, Address 0x5F)

    35
  • Configuration Error Register (CFG_ERROR, Address 0x60)

    35
• Outline Dimensions

  36
• Ordering Guide

  36