データシート (AD9129-MIX-EBZ)目次Features1Applications1Functional Block Diagram1General Description1Product Highlights1Revision History2Specifications3DC Specifications3LVDS Digital Specifications4HSTL Digital Specifications4Serial Port and CMOS Pin Specifications5AC Specifications6Absolute Maximum Ratings7Thermal Resistance7ESD Caution7Pin Configurations and Function Descriptions8Typical Performance Characteristics12AD911912Static Linearity12AC (Normal Mode)13AC (Mix-Mode)16DOCSIS Performance (Normal Mode)19AD912922Static Linearity22AC (Normal Mode)23AC (Mix-Mode)27DOCSIS Performance (Normal Mode)31Terminology35Serial Communications Port Overview36Serial Peripheral Interface (SPI)36General Operation of the SPI36Instruction Mode (8-Bit Instruction)36Serial Peripheral Interface Pin Descriptions36SCLK—Serial Clock36—Chip Select36SDIO—Serial Data I/O36SDO—Serial Data Out36MSB/LSB Transfers37Serial Port Configuration37Theory of Operation38LVDS Data Port Interface39Temperature Effects41Parity41Digital Datapath Description42FIFO Description43Resetting the FIFO Data Level43Monitoring the FIFO Status43Multiple DAC Synchronization43Data Assembler and Signal Processing Modes452× Digital Filter45Pipeline Delay (Latency)46Power-Up Time46Interrupt Requests47Interface Timing Validation48Sample Error Detection (SED) Operation48SED Example48Normal Operation48Analog Interface Considerations49Analog Modes of Operation49Clock Input50PLL50Voltage Reference51Analog Outputs51Equivalent DAC Output and Transfer Function51Peak DAC Output Power Capability52Output Stage Configuration52Start-Up Sequence54Device Configuration Registers55Device Configuration Register Map55Device Configuration Register Descriptions56SPI Communications Control Register56Power Control Register56Interrupt Enable Register 057Interrupt Enable Register 157Interrupt Status Register 057Interrupt Status Register158Frame Pin Usage Register58Reserved_0 Register58Data Receiver Control 0 Register58Data Receiver Control 1 Register59Data Receiver Control 2 Register59Data Receiver Control 3 Register59Data Receiver Status 0 Register59FIFO Control Register60FIFO Offset Register60FIFO Thermometer for Phase 0 Status Register60FIFO Thermometer for Phase 1 Status Register60FIFO Thermometer for Phase 2 Status Register60FIFO Thermometer for Phase 3 Status Register60Data Mode Control Register61Decoder Control (Program Thermometer Type) Register61Sync Control Register61Full-Scale Current Adjust (Lower) Register61Full-Scale Current Adjust (Upper) Register61Analog Control 1 Register62Analog Control 2 Register62Clock Control 1 Register62Retimer Control 0 Register62Retimer Control 1 Register62Retimer Status 0 Register62Sample Error Detection (SED) Control Register63Sample Error Detection (SED) Data Port 0 Rising Edge Status Low Register63Sample Error Detection (SED) Data Port 0 Rising Edge Status High Register63Sample Error Detection (SED) Data Port 1 Rising Edge Status Low Register63Sample Error Detection (SED) Data Port 1 Rising Edge Status High Register63Sample Error Detection (SED) Data Port 0 Falling Edge Status Low Register64Sample Error Detection (SED) Data Port 0 Falling Edge Status High Register64Sample Error Detection (SED) Data Port 1 Falling Edge Status Low Register64Sample Error Detection (SED) Data Port 1 Falling Edge Status High Register64Parity Control Register64Parity Rising Edge Count Register64Parity Falling Edge Count Register64Delay Control Register 065Delay Control Register 165Drive Strength Register65Part ID Register65Outline Dimensions66Ordering Guide66サイズ： 2.69MBページ数： 68Language: Englishマニュアルを開く
