Analog Devices AD9253 Evaluation Board AD9253-125EBZ マニュアル

目次

• FEATURES

  1
• APPLICATIONS

  1
• GENERAL DESCRIPTION

  1
• FUNCTIONAL BLOCK DIAGRAM

  1
• PRODUCT HIGHLIGHTS

  1
• TABLE OF CONTENTS

  2
• REVISION HISTORY

  2
• SPECIFICATIONS

  3
  • DC SPECIFICATIONS

    3
  • AC SPECIFICATIONS

    4
  • DIGITAL SPECIFICATIONS

    5
  • SWITCHING SPECIFICATIONS

    6
  • TIMING SPECIFICATIONS

    6
    • Timing Diagrams

      7
• ABSOLUTE MAXIMUM RATINGS

  11
  • THERMAL RESISTANCE

    11
  • ESD CAUTION

    11
• PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

  12
• TYPICAL PERFORMANCE CHARACTERISTICS

  14
  • AD9253-80

    14
  • AD9253-105

    16
  • AD9253-125

    18
• EQUIVALENT CIRCUITS

  21
• THEORY OF OPERATION

  22
  • ANALOG INPUT CONSIDERATIONS

    22
    • Input Common Mode

      22
    • Differential Input Configurations

      23
  • VOLTAGE REFERENCE

    23
    • Internal Reference Connection

      23
    • External Reference Operation

      24
  • CLOCK INPUT CONSIDERATIONS

    24
    • Clock Input Options

      24
    • Input Clock Divider

      25
    • Clock Duty Cycle

      25
    • Jitter Considerations

      26
  • POWER DISSIPATION AND POWER-DOWN MODE

    26
  • DIGITAL OUTPUTS AND TIMING

    27
    • SDIO/OLM Pin

      30
    • SCLK/DTP Pin

      30
    • CSB Pin

      30
    • RBIAS Pin

      30
  • OUTPUT TEST MODES

    30
• SERIAL PORT INTERFACE (SPI)

  31
  • CONFIGURATION USING THE SPI

    31
  • HARDWARE INTERFACE

    32
  • CONFIGURATION WITHOUT THE SPI

    32
  • SPI ACCESSIBLE FEATURES

    32
• MEMORY MAP

  33
  • READING THE MEMORY MAP REGISTER TABLE

    33
    • Open Locations

      33
    • Default Values

      33
    • Logic Levels

      33
    • Channel-Specific Registers

      33
  • MEMORY MAP REGISTER TABLE

    34
  • MEMORY MAP REGISTER DESCRIPTIONS

    37
    • Device Index (Register 0x05)

      37
    • Transfer (Register 0xFF)

      37
    • Power Modes (Register 0x08)

      37
      • Bits[7:6]—Open

        37
      • Bit 5—External Power-Down Pin Function

        37
      • Bits[4:2]—Open

        37
      • Bits[1:0]—Power Mode

        37
    • Enhancement Control (Register 0x0C)

      37
      • Bits[7:3]—Open

        37
      • Bit 2—Chop Mode

        37
      • Bits[1:0]—Open

        37
    • Output Mode (Register 0x14)

      37
      • Bit 7—Open

        37
      • Bit 6—LVDS-ANSI/LVDS-IEEE Option

        37
      • Bits[5:3]—Open

        37
      • Bit 2—Output Invert

        37
      • Bit 1—Open

        37
      • Bit 0—Output Format

        37
    • Output Adjust (Register 0x15)

      37
      • Bits[7:6]—Open

        37
      • Bits[5:4]—Output Driver Termination

        37
      • Bits[3:1]—Open

        37
      • Bit 0—Output Drive

        37
    • Output Phase (Register 0x16)

      37
      • Bit 7—Open

        37
      • Bits[6:4]—Input Clock Phase Adjust

        37
      • Bits[3:0]—Output Clock Phase Adjust

        38
    • Serial Output Data Control (Register 0x21)

      38
    • Resolution/Sample Rate Override (Register 0x100)

      38
    • User I/O Control 2 (Register 0x101)

      38
      • Bits[7:1]—Open

        38
      • Bit 0—SDIO Pull-Down

        38
    • User I/O Control 3 (Register 0x102)

      38
      • Bits[7:4]—Open

        38
      • Bit 3—VCM Power-Down

        38
      • Bits[2:0]—Open

        38
• APPLICATIONS INFORMATION

  39
  • DESIGN GUIDELINES

    39
  • POWER AND GROUND RECOMMENDATIONS

    39
  • EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS

    39
  • VCM

    39
  • REFERENCE DECOUPLING

    39
  • SPI PORT

    39
  • CROSSTALK PERFORMANCE

    39
• OUTLINE DIMENSIONS

  40
  • ORDERING GUIDE

    40