Analog Devices AD9279 Evaluation Board AD9279-65EBZ マニュアル

目次

• FEATURES

  1
• GENERAL DESCRIPTION

  1
• FUNCTIONAL BLOCK DIAGRAM

  1
• TABLE OF CONTENTS

  2
• REVISION HISTORY

  2
• SPECIFICATIONS

  3
  • AC SPECIFICATIONS

    3
  • DIGITAL SPECIFICATIONS

    6
  • SWITCHING SPECIFICATIONS

    7
  • ADC TIMING DIAGRAMS

    8
• ABSOLUTE MAXIMUM RATINGS

  9
  • THERMAL IMPEDANCE

    9
  • ESD CAUTION

    9
• PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

  10
• TYPICAL PERFORMANCE CHARACTERISTICS

  13
  • TGC MODE

    13
  • CW DOPPLER MODE

    16
• EQUIVALENT CIRCUITS

  17
• ULTRASOUND THEORY OF OPERATION

  19
• CHANNEL OVERVIEW

  20
  • TGC OPERATION

    20
    • Low Noise Amplifier (LNA)

      23
      • Active Impedance Matching

        23
      • LNA Noise

        24
      • Input Overdrive

        25
    • Variable Gain Amplifier (VGA)

      26
      • Gain Control

        26
      • VGA Noise

        26
    • Antialiasing Filter (AAF)

      26
    • ADC

      27
      • Clock Input Considerations

        27
      • Clock Duty Cycle Considerations

        28
      • Clock Jitter Considerations

        28
    • Power Dissipation and Power-Down Mode

      28
    • Power and Ground Recommendations

      29
    • Digital Outputs and Timing

      29
      • SDIO Pin

        33
      • SCLK Pin

        33
      • CSB Pin

        33
    • RBIAS Pin

      33
    • Voltage Reference

      33
  • CW DOPPLER OPERATION

    33
    • Quadrature Generation

      33
    • I/Q Demodulator and Phase Shifter

      34
    • Dynamic Range and Noise

      34
    • Phase Compensation and Analog Beamforming

      35
    • CW Application Information

      36
• SERIAL PORT INTERFACE (SPI)

  37
  • HARDWARE INTERFACE

    37
• MEMORY MAP

  39
  • READING THE MEMORY MAP TABLE

    39
  • RESERVED LOCATIONS

    39
  • DEFAULT VALUES

    39
  • LOGIC LEVELS

    39
• OUTLINE DIMENSIONS

  43
  • ORDERING GUIDE

    43