Analog Devices AD9629 Evaluation Board AD9629-40EBZ マニュアル

目次

• FEATURES

  1
• APPLICATIONS

  1
• FUNCTIONAL BLOCK DIAGRAM

  1
• PRODUCT HIGHLIGHTS

  1
• TABLE OF CONTENTS

  2
• REVISION HISTORY

  2
• GENERAL DESCRIPTION

  3
• SPECIFICATIONS

  4
  • DC SPECIFICATIONS

    4
  • AC SPECIFICATIONS

    5
  • DIGITAL SPECIFICATIONS

    6
  • SWITCHING SPECIFICATIONS

    7
  • TIMING SPECIFICATIONS

    8
• ABSOLUTE MAXIMUM RATINGS

  9
  • THERMAL CHARACTERISTICS

    9
  • ESD CAUTION

    9
• PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

  10
• TYPICAL PERFORMANCE CHARACTERISTICS

  11
  • AD9629-80

    11
  • AD9629-65

    13
  • AD9629-40

    14
  • AD9629-20

    15
• EQUIVALENT CIRCUITS

  16
• THEORY OF OPERATION

  17
  • ANALOG INPUT CONSIDERATIONS

    17
    • Input Common Mode

      17
    • Differential Input Configurations

      18
    • Single-Ended Input Configuration

      18
  • VOLTAGE REFERENCE

    19
    • Internal Reference Connection

      19
    • External Reference Operation

      19
  • CLOCK INPUT CONSIDERATIONS

    20
    • Clock Input Options

      20
    • Input Clock Divider

      20
    • Clock Duty Cycle

      21
    • Jitter Considerations

      21
  • POWER DISSIPATION AND STANDBY MODE

    21
  • DIGITAL OUTPUTS

    22
    • Digital Output Enable Function (OEB)

      22
  • TIMING

    22
    • Data Clock Output (DCO)

      22
• BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST

  23
  • BUILT-IN SELF-TEST (BIST)

    23
  • OUTPUT TEST MODES

    23
• SERIAL PORT INTERFACE (SPI)

  24
  • CONFIGURATION USING THE SPI

    24
  • HARDWARE INTERFACE

    25
  • CONFIGURATION WITHOUT THE SPI

    25
  • SPI ACCESSIBLE FEATURES

    25
• MEMORY MAP

  26
  • READING THE MEMORY MAP REGISTER TABLE

    26
  • OPEN LOCATIONS

    26
  • DEFAULT VALUES

    26
    • Logic Levels

      26
    • Transfer Register Map

      26
  • MEMORY MAP REGISTER TABLE

    27
  • MEMORY MAP REGISTER DESCRIPTIONS

    29
    • USR2 (Register 0x101)

      29
    • Bit 3—Enable GCLK Detect

      29
    • Bit 2—Run GCLK

      29
    • Bit 0—Disable SDIO Pull-Down

      29
• APPLICATIONS INFORMATION

  30
  • DESIGN GUIDELINES

    30
    • Power and Ground Recommendations

      30
    • Exposed Paddle Thermal Heat Sink Recommendations

      30
    • VCM

      30
    • RBIAS

      30
    • Reference Decoupling

      30
    • SPI Port

      30
• OUTLINE DIMENSIONS

  31
  • ORDERING GUIDE

    31