Analog Devices AD9640 Evaluation Board AD9640-80EBZ マニュアル

目次

• FEATURES

  1
• APPLICATIONS

  1
• FUNCTIONAL BLOCK DIAGRAM

  1
• PRODUCT HIGHLIGHTS

  1
• TABLE OF CONTENTS

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• REVISION HISTORY

  3
• GENERAL DESCRIPTION

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• SPECIFICATIONS

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  • ADC DC SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ80, AD9640ABCPZ-105, AND AD9640BCPZ-105

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  • ADC DC SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ125, AD9640ABCPZ-150, AND AD9640BCPZ150

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  • ADC AC SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ80, AD9640ABCPZ-105, AND AD9640BCPZ-105

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  • ADC AC SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ125, AD9640ABCPZ-150, AND AD9640BCPZ 150

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  • DIGITAL SPECIFICATIONS

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  • SWITCHING SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ-80, AD9640ABCPZ-105, AND AD9640BCPZ105

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  • SWITCHING SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ-125, AD9640ABCPZ-150, AND AD9640BCPZ150

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  • TIMING SPECIFICATIONS

    12
    • Timing Diagrams

      12
• ABSOLUTE MAXIMUM RATINGS

  14
  • THERMAL CHARACTERISTICS

    14
  • ESD CAUTION

    14
• PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

  15
• EQUIVALENT CIRCUITS

  19
• TYPICAL PERFORMANCE CHARACTERISTICS

  20
• THEORY OF OPERATION

  25
  • ADC ARCHITECTURE

    25
  • ANALOG INPUT CONSIDERATIONS

    25
    • Input Common Mode

      25
    • Differential Input Configurations

      25
    • Single-Ended Input Configuration

      26
  • VOLTAGE REFERENCE

    27
    • Internal Reference Connection

      27
    • External Reference Operation

      27
  • CLOCK INPUT CONSIDERATIONS

    28
    • Clock Input Options

      28
    • Input Clock Divider

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    • Clock Duty Cycle

      29
    • Jitter Considerations

      29
  • POWER DISSIPATION AND STANDBY MODE

    30
  • DIGITAL OUTPUTS

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    • Digital Output Enable Function (OEB)

      31
  • TIMING

    31
    • Data Clock Output (DCO)

      31
• ADC OVERRANGE AND GAIN CONTROL

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  • FAST DETECT OVERVIEW

    32
  • ADC FAST MAGNITUDE

    32
  • ADC OVERRANGE (OR)

    33
  • GAIN SWITCHING

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    • Coarse Upper Threshold (C_UT)

      33
    • Fine Upper Threshold (F_UT)

      33
    • Fine Lower Threshold (F_LT)

      33
    • Increment Gain (IG) and Decrement Gain (DG)

      33
• SIGNAL MONITOR

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  • PEAK DETECTOR MODE

    35
  • RMS/MS MAGNITUDE MODE

    35
  • THRESHOLD CROSSING MODE

    36
  • ADDITIONAL CONTROL BITS

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    • Signal Monitor Enable Bit

      36
    • Complex Power Calculation Mode Enable Bit

      36
  • DC CORRECTION

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    • DC Correction Bandwidth

      37
    • DC Correction Readback

      37
    • DC Correction Freeze

      37
    • DC Correction Enable Bits

      37
  • SIGNAL MONITOR SPORT OUTPUT

    37
    • SMI SCLK

      37
    • SMI SDFS

      37
    • SMI SDO

      37
• BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST

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  • BUILT-IN SELF-TEST (BIST)

    38
  • OUTPUT TEST MODES

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• CHANNEL/CHIP SYNCHRONIZATION

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• SERIAL PORT INTERFACE (SPI)

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  • CONFIGURATION USING THE SPI

    40
  • HARDWARE INTERFACE

    40
  • CONFIGURATION WITHOUT THE SPI

    41
  • SPI ACCESSIBLE FEATURES

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• MEMORY MAP

  42
  • READING THE MEMORY MAP TABLE

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    • Open Locations

      42
    • Default Values

      42
    • Logic Levels

      42
    • Transfer Register Map

      42
    • Channel-Specific Registers

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  • EXTERNAL MEMORY MAP

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  • MEMORY MAP REGISTER DESCRIPTION

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    • Sync Control (Register 0x100)

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      • Bit 7—Signal Monitor Sync Enable

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      • Bits[6:3]—Reserved

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      • Bit 2—Clock Divider Next Sync Only

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      • Bit 1—Clock Divider Sync Enable

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      • Bit 0—Master Sync Enable

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    • Fast Detect Control (Register 0x104)

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      • Bits[7:4]—Reserved

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      • Bits[3:1]—Fast Detect Mode Select

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      • Bit 0—Fast Detect Enable

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    • Fine Upper Threshold (Register 0x106 and Register 0x107)

      46
      • Register 0x106, Bits[7:0]—Fine Upper Threshold[7:0]

        46
      • Register 0x107, Bits[7:5]—Reserved

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      • Register 0x107, Bits[4:0]—Fine Upper Threshold[12:8]

        46
    • Fine Lower Threshold (Register 0x108 and Register 0x109)

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      • Register 0x108, Bits[7:0]—Fine Lower Threshold[7:0]Register 0x109, Bits[7:5]—ReservedRegister 0x109, Bits[4:0]—Fine Lower Threshold[12:8]

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    • Signal Monitor DC Correction Control (Register 0x10C)

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      • Bit 7—ReservedBit 6—DC Correction Freeze

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      • Bits[5:2]—DC Correction Bandwidth

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      • Bit 1—DC Correction for Signal Path Enable

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      • Bit 0—DC Correction for SM Enable

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    • Signal Monitor DC Value Channel A (Register 0x10D and Register 0x10E)

      47
      • Register 0x10D, Bits[7:0]—Channel A DC Value[7:0]

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      • Register 0x10E, Bits[7:0]—Channel A DC Value[13:8]

        47
    • Signal Monitor DC Value Channel B (Register 0x10F and Register 0x110)

      47
      • Register 0x10F Bits[7:0]—Channel B DC Value[7:0]

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      • Register 0x110 Bits[7:0]—Channel B DC Value[13:8]

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    • Signal Monitor SPORT Control (Register 0x111)

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      • Bit 7—Reserved

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      • Bit 6—RMS/MS Magnitude Output Enable

        47
      • Bit 5—Peak Power Output Enable

        47
      • Bit 4—Threshold Crossing Output Enable

        47
      • Bits[3:2]—SPORT SMI SCLK Divide

        47
      • Bit 1— SPORT SMI SCLK Sleep

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      • Bit 0—Signal Monitor SPORT Output Enable

        47
    • Signal Monitor Control (Register 0x112)

      47
      • Bit 7—Complex Power Calculation Mode Enable

        47
      • Bits[6:4]—Reserved

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      • Bit 3—Signal Monitor RMS/MS Select

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      • Bits[2:1]—Signal Monitor Mode

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      • Bit 0—Signal Monitor Enable

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    • Signal Monitor Period (Register 0x113 to Register 0x115)

      47
      • Register 0x113, Bits[7:0]—Signal Monitor Period[7:0]

        47
      • Register 0x114, Bits[7:0]—Signal Monitor Period[15:8]

        47
      • Register 0x115, Bits[7:0]—Signal Monitor Period[23:16]

        47
    • Signal Monitor Result Channel A (Register 0x116 to Register 0x118)

      48
      • Register 0x116, Bits[7:0]—Signal Monitor Result Channel A[7:0]

        48
      • Register 0x117, Bits[7:0]—Signal Monitor Result Channel A[15:8]

        48
      • Register 0x118, Bits[7:4]—Reserved

        48
      • Register 0x118, Bits[3:0]—Signal Monitor Result Channel A[19:16]

        48
    • Signal Monitor Result Channel B (Register 0x119 to Register 0x11B)

      48
      • Register 0x119, Bits[7:0]— Signal Monitor Result Channel B[7:0]

        48
      • Register 0x11A, Bits[7:0]—Signal Monitor Result Channel B[15:8]

        48
      • Register 0x11B, Bits[7:4]—Reserved

        48
      • Register 0x11B, Bits[3:0]—Signal Monitor Result Channel B[19:16]

        48
• APPLICATIONS INFORMATION

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  • DESIGN GUIDELINES

    49
    • Power and Ground Recommendations

      49
    • LVDS Operation

      49
    • Exposed Paddle Thermal Heat Slug Recommendations

      49
    • CML

      49
    • RBIAS

      49
    • Reference Decoupling

      49
    • SPI Port

      49
• OUTLINE DIMENSIONS

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  • ORDERING GUIDE

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