データシート (EV-ADF4157SD1Z)目次Features1Applications1General Description1Functional Block Diagram1Revision History2Specifications3Timing Specifications4Absolute Maximum Ratings5Thermal Resistance5ESD Caution5Pin Configurations and Function Descriptions6Typical Performance Characteristics8Circuit Description9Reference Input Section9RF Input Stage9RF INT Divider925-Bit Fixed Modulus9INT, FRAC, and R Relationship9RF R Counter9Phase Frequency Detector (PFD) and Charge Pump10MUXOUT and Lock Detect10Input Shift Register10Program Modes10Register Maps11FRAC/INT Register (R0) Map12Reserved Bit12MUXOUT1212-Bit INT Value1212-Bit MSB FRAC Value12LSB FRAC Register (R1) Map1313-Bit LSB FRAC Value13Reserved Bits13R Divider Register (R2) Map14CSR Enable14Charge Pump Current Setting14Prescaler (P/P + 1)14RDIV214Reference Doubler145-Bit R Counter14Reserved Bits14Function Register (R3) Map16Reserved Bits16Σ-Δ Reset16Lock Detect Precision (LDP)16Phase Detector Polarity16RF Power-Down16RF Charge Pump Three-State16RF Counter Reset16Test Register (R4) Map17Negative Bleed Current17CLK Divider Mode1712-Bit Clock Divider Value17Reserved Bits17Applications Information18Initialization Sequence18RF Synthesizer: A Worked Example18Reference Doubler and Reference Divider18Cycle Slip Reduction for Faster Lock Times18Cycle Slips18Fastlock Timer and Register Sequences19Fastlock: An Example19Fastlock: Loop Filter Topology19Spur Mechanisms19Fractional Spurs19Integer Boundary Spurs19Reference Spurs19Low Frequency Applications20Filter Design—ADIsimPLL20Operating with Wide Loop Filter Bandwidths20PCB Design Guidelines for the Chip Scale Package20Outline Dimensions21Ordering Guide21サイズ： 341KBページ数： 24Language: Englishマニュアルを開く
