Atmel SpaceWire Router SpW-10X マニュアル

目次

• CONTENTS

  4
• LIST OF FIGURES

  10
• LIST OF TABLES

  12
• INTRODUCTION

  14
• TERMS, ACRONYMS AND ABBREVIATIONS

  14
• DOCUMENTS

  15
• USER APPLICATIONS

  16
• STAND-ALONE ROUTER

  16
• NODE INTERFACE

  17
• EMBEDDED ROUTER

  17
• EXPANDING THE NUMBER OF ROUTER PORTS

  18
• FUNCTIONAL OVERVIEW

  21
• SPACEWIRE PORTS

  22
• EXTERNAL PORTS

  22
• CONFIGURATION PORT

  23
• ROUTING TABLE

  23
• ROUTING CONTROL LOGIC AND CROSSBAR

  23
• TIME-CODE PROCESSING

  24
• CONTROL/STATUS REGISTERS

  24
• PIN LOCATIONS

  25
• DEVICE INTERFACE

  31
• GLOBAL SIGNALS

  31
• 5.2 SPACEWIRE SIGNALS

  32
• 5.2.1 SpW-10X SpaceWire Signals

  32
• 5.2.2 SpaceWire Input Fail Safe Resistors

  35
• 5.2.3 Operation with 5V Powered LVDS Devices

  37
• EXTERNAL PORT DATA SIGNALS

  37
• TIME-CODE SIGNALS

  39
• STATUS INTERFACE SIGNALS

  41
• RESET CONFIGURATION SIGNALS

  42
• 5.7 POWER, GROUND, PLL AND LVDS SIGNALS

  45
• 5.7.1 General

  45
• 5.7.2 Decoupling

  45
• 5.7.3 LVDS Reference

  45
• 5.7.4 PLL External Components

  45
• INTERFACE OPERATIONS

  47
• EXTERNAL PORT INTERFACE OPERATION

  47
• TIME-CODE INTERFACE OPERATION

  48
• STATUS INTERFACE OPERATION

  49
• RESET CONFIGURATION INTERFACE OPERATION

  51
• SPACEWIRE ROUTER PACKET TYPES

  52
• PACKET ADDRESSES

  52
• PACKET PRIORITY

  53
• PACKET HEADER DELETION

  53
• INVALID ADDRESSES

  54
• DATA PACKETS

  55
• 7.6 COMMAND PACKETS

  55
• 7.6.1 Supported Commands

  55
• 7.6.2 Read Command

  56
• 7.6.3 Read Incrementing Command

  60
• 7.6.4 Read Modify Write Command

  65
• 7.6.5 Write Command

  70
• 7.6.6 Command Error Response

  74
• 7.6.7 Command Packet Cyclic Redundancy Check

  76
• 7.6.8 Local Source Path Address

  76
• 7.6.9 Source Path Address Field

  77
• 7.6.10 Command Packet Fill Bytes

  78
• CONTROL LOGIC AND OPERATIONAL MODES

  79
• 8.1 SPACEWIRE LINK CONTROL

  79
• 8.1.1 Default operating mode

  79
• Auto-Start

  79
• Link-Start

  79
• Link-Disable

  80
• Automatic deactivate driver mode

  80
• Setting the SpaceWire port transmit data rate

  82
• 8.2 GLOBAL SPACEWIRE LINK CONTROL

  84
• 8.2.1 Start on request mode

  85
• 8.2.2 Disable on Silence mode

  85
• 8.3 CONTROL LOGIC AND ROUTING

  86
• 8.3.1 Packet address error

  86
• 8.3.2 Arbitration

  86
• 8.3.2.1 Arbitration of packets with matching priority (1)

  87
• 8.3.2.2 Arbitration of packets with matching priority (2)

  88
• 8.3.2.3 Arbitration of packets with different priority (1)

  89
• 8.3.2.4 Arbitration of packets with different priority (2)

  90
• 8.3.3 Group Adaptive Routing

  92
• 8.3.3.1 Normal Group adaptive routing

  92
• 8.3.3.2 Group adaptive routing when busy

  92
• 8.3.3.3 Group adaptive routing when ports not ready

  93
• 8.3.4 Loop-back with Self-Addressing

  93
• 8.3.5 Packet Blocking

  95
• 8.3.5.1 Blocked destination

  95
• 8.3.5.2 Stalled source

  98
• 8.3.5.3 Waiting for an output port

  101
• REGISTER DEFINITIONS

  103
• INTERNAL MEMORY MAP

  103
• REGISTER ADDRESSES SUMMARY

  104
• GROUP ADAPTIVE ROUTING TABLE REGISTERS

  105
• 9.4 PORT CONTROL/STATUS REGISTERS

  108
• 9.4.1 Generic port control/status register fields.

  108
• 9.4.2 Configuration port control/status register fields.

  109
• 9.4.3 SpaceWire port control/status register bits.

  112
• 9.4.4 External port control/status register bits

  115
• 9.5 ROUTER CONTROL/STATUS REGISTERS

  115
• 9.5.1 Network Discovery Register

  115
• 9.5.2 Router Identity Register

  116
• 9.5.3 Router Control Register

  117
• 9.5.4 Error active Register

  120
• Time-Code Register

  121
• Device Manufacturer and Chip ID Register

  122
• General Purpose Register

  123
• Time-Code Enable Register

  123
• Transmit Clock Control Register

  124
• Destination Key Register

  127
• Unused Registers and Register Bits

  127
• Empty packets

  127
• WRITING TO A READ-ONLY REGISTER

  127
• SWITCHING CHARACTERISTICS

  128
• CLOCK AND RESET TIMING PARAMETERS

  128
• SERIAL SIGNALS TIMING PARAMETERS

  128
• EXTERNAL PORT TIMING PARAMETERS

  129
• TIME-CODE INTERFACE TIMING PARAMETERS

  130
• ERROR/STATUS INTERFACE TIMING PARAMETERS

  131
• 10.6 LATENCY AND JITTER

  133
• 10.6.1 Clock Periods

  133
• 10.6.2 Switching Latency

  133
• 10.6.3 Router Latency

  133
• 10.6.4 Time-code Latency

  134
• 10.6.5 Time-code Jitter

  135
• 10.6.6 200M bits/s Input and Output Bit Rate Example

  135
• ELECTRICAL CHARACTERISTICS

  136
• DC CHARACTERISTICS

  136
• ABSOLUTE MAXIMUM RATINGS

  137
• RELIABILITY INFORMATION

  137
• APPLICATION GUIDELINES

  138
• EXAMPLE CIRCUIT DIAGRAM

  138
• 12.2 PCB DESIGN AND LAYOUT GUIDELINES

  140
• 12.2.1 CLK

  140
• 12.2.2 RST_N

  140
• 12.2.3 Chip Test Signals

  140
• 12.2.4 Power and Decoupling

  140
• 12.2.5 Ground

  140
• 12.2.6 SpaceWire

  140
• 12.2.7 External Ports

  141
• 12.2.8 Time-code Interface

  141
• 12.2.9 Status / Power On Configuration Interface

  141
• 12.2.10 PLL

  142
• ANOMALIES AND WARNINGS

  143
• ANOMALIES

  143
• WARNINGS

  143
• 13.3 RESET ANOMALY

  145
• 13.3.1 Data Strobe Reset Waveform

  145
• 13.3.2 Data Strobe Disable Waveform

  147
• 13.3.3 Reset Anomaly Workarounds

  147
• 13.4 PARITY ERROR ANOMALY

  148
• 13.4.1 Parity Error Action

  148
• 13.4.2 Parity Error Anomaly

  148
• 13.4.3 Parity Error Workaround

  149
• TECHNICAL SUPPORT

  150
• DOCUMENT CHANGES

  151
• ISSUE 3.3 TO ISSUE 3.4

  151
• ISSUE 3.2 TO ISSUE 3.3

  151
• ISSUE 3.1 TO ISSUE 3.2

  151
• ISSUE 3.0 TO ISSUE 3.1

  152
• ISSUE 2.5 TO ISSUE 3.0

  152
• ISSUE 2.4 TO ISSUE 2.5

  153
• ISSUE 2.3 TO ISSUE 2.4

  153
• ISSUE 2.2 TO ISSUE 2.3

  153
• ISSUE 2.1 TO ISSUE 2.2

  154
• ISSUE 2.0 TO ISSUE 2.1

  154
• ISSUE 1.7 TO ISSUE 2.0

  154
• ISSUE 1.6 TO ISSUE 1.7

  154
• ISSUE 1.5 TO ISSUE 1.6

  154
• ISSUE 1.4 TO ISSUE 1.5

  154
• ISSUE 1.3 TO ISSUE 1.4

  154
• ISSUE 1.2 TO ISSUE 1.3

  154
• ISSUE 1.1 TO ISSUE 1.2

  155
• ISSUE 1.0 TO ISSUE 1.1

  155
• FIGURE 2-1 STAND-ALONE ROUTER

  16
• FIGURE 2-2 NODE INTERFACE

  17
• FIGURE 2-3 EMBEDDED ROUTER

  18
• FIGURE 2-4 EXPANDING THE NUMBER OF SPACEWIRE PORTS (1)

  19
• FIGURE 2-5 EXPANDING THE NUMBER OF SPACEWIRE PORTS (2)

  20
• FIGURE 3-1 SPACEWIRE ROUTER BLOCK DIAGRAM

  22
• FIGURE 5-1 LVDS RECEIVER FAIL-SAFE RESISTORS

  35
• FIGURE 5-2 CONFIGURATION INTERFACE TIMING SPECIFICATION

  42
• FIGURE 5-3 PLL WITH EXTERNAL COMPONENTS

  46
• FIGURE 6-1 EXTERNAL PORT WRITE TIMING SPECIFICATION

  47
• FIGURE 6-2 EXTERNAL PORT READ TIMING SPECIFICATION

  48
• FIGURE 6-3 TIME-CODE INPUT INTERFACE

  48
• FIGURE 6-4 TIME-CODE OUTPUT INTERFACE

  49
• FIGURE 6-5 TIME-CODE RESET INTERFACE

  49
• FIGURE 6-6 STATUS MULTIPLEXER OUTPUT INTERFACE

  49
• FIGURE 6-7 RESET CONFIGURATION INTERFACE TIMING SPECIFICATION

  51
• FIGURE 7-1 NORMAL ROUTER DATA PACKETS

  55
• FIGURE 7-2 COMMAND PACKET FORMAT

  55
• FIGURE 7-3 READ SINGLE ADDRESS COMMAND FORMAT

  57
• FIGURE 7-4 READ SINGLE ADDRESS REPLY PACKET FORMAT

  59
• FIGURE 7-5 READ INCREMENTING ADDRESS COMMAND FORMAT

  62
• FIGURE 7-6 READ INCREMENTING ADDRESS REPLY PACKET FORMAT

  64
• FIGURE 7-7 READ-MODIFY-WRITE COMMAND PACKET FORMAT

  66
• FIGURE 7-8 READ-MODIFY-WRITE EXAMPLE OPERATION

  68
• FIGURE 7-9 READ-MODIFY-WRITE REPLY PACKET FORMAT

  69
• FIGURE 7-10 WRITE SINGLE ADDRESS COMMAND PACKET

  71
• FIGURE 7-11 WRITE SINGLE ADDRESS REPLY PACKET

  73
• FIGURE 7-12 SOURCE PATH ADDRESS FIELD DECODING

  78
• FIGURE 7-13 SOURCE PATH ADDRESSES IN REPLY PACKET

  78
• FIGURE 7-14 NORMAL CONFIGURATION PACKET HEADER STRUCTURE

  78
• FIGURE 7-15 FILL BYTES CONFIGURATION HEADER STRUCTURE

  78
• FIGURE 8-1 DEACTIVATE DRIVER OPERATING MODE

  81
• FIGURE 8-2 DEACTIVATED LDVS DRIVER OUTPUT

  81
• FIGURE 8-4 START ON REQUEST MODE

  85
• FIGURE 8-5 DISABLE ON SILENCE MODE

  86
• FIGURE 8-6 ARBITRATION OF TWO PACKETS WITH MATCHING PRIORITY.

  87
• FIGURE 8-7 ARBITRATION OF THREE PACKETS WITH MATCHING PRIORITY

  88
• FIGURE 8-8 ARBITRATION OF TWO PACKETS WITH DIFFERENT PRIORITY (1)

  89
• FIGURE 8-9 ARBITRATION OF TWO PACKETS WITH DIFFERENT PRIORITY (2)

  91
• FIGURE 8-10 NORMAL GROUP ADAPTIVE ROUTING

  92
• FIGURE 8-11 GROUP ADAPTIVE ROUTING WHEN OTHER PORTS BUSY

  93
• FIGURE 8-12 GROUP ADAPTIVE ROUTING WHEN PORTS NOT READY

  93
• FIGURE 8-13 PACKET SELF-ADDRESSING MODE

  94
• FIGURE 8-14 DESTINATION NODE BLOCKED (A)

  96
• FIGURE 8-15 DESTINATION NODE BLOCKED (B)

  96
• FIGURE 8-16 DESTINATION NODE BLOCKED (C)

  97
• FIGURE 8-17 DESTINATION NODE BLOCKED: WATCHDOG MODE (A)

  97
• FIGURE 8-18 DESTINATION NODE BLOCKED: WATCHDOG MODE (B)

  97
• FIGURE 8-19 DESTINATION NODE BLOCKED: WATCHDOG MODE (C)

  98
• FIGURE 8-20 DESTINATION NODE BLOCKED: WATCHDOG MODE (D)

  98
• FIGURE 8-21 SOURCE NODE STALLED (A)

  99
• FIGURE 8-22 SOURCE NODE STALLED (B)

  99
• FIGURE 8-23 SOURCE NODE STALLED (C)

  99
• FIGURE 8-24 SOURCE NODE STALLED (D)

  99
• FIGURE 8-25 SOURCE NODE STALLED: WATCHDOG MODE (A)

  100
• FIGURE 8-26 SOURCE NODE STALLED: WATCHDOG MODE (B)

  100
• FIGURE 8-27 SOURCE NODE STALLED: WATCHDOG MODE (C)

  100
• FIGURE 8-28 SOURCE NODE STALLED: WATCHDOG MODE (D)

  100
• FIGURE 9-1 ROUTER INTERNAL MEMORY MAP

  103
• FIGURE 9-2 GAR REGISTER FIELDS

  105
• FIGURE 9-3 SPACEWIRE PORT CONTROL/STATUS REGISTER FIELDS

  112
• FIGURE 9-4 NETWORK DISCOVERY REGISTER FIELDS

  116
• FIGURE 9-5 ROUTER CONTROL REGISTER FIELDS

  117
• FIGURE 9-6 ERROR ACTIVE REGISTER FIELDS

  120
• FIGURE 9-7 TIME-CODE REGISTER FIELDS

  121
• FIGURE 9-8 DEVICE MANUFACTURER AND CHIP ID REGISTER FIELDS

  122
• FIGURE 9-9 TIME-CODE ENABLE REGISTER FIELDS

  123
• FIGURE 9-10 TRANSMIT CLOCK CONTROL REGISTER

  125
• FIGURE 10-1 DS MINIMUM CONSECUTIVE EDGE SEPARATION

  128
• FIGURE 10-2 EXTERNAL PORT INPUT FIFO TIMING PARAMETERS

  129
• FIGURE 10-3 EXTERNAL PORT OUTPUT FIFO TIMING PARAMETERS

  129
• FIGURE 10-4 TIME-CODE INPUT INTERFACE

  130
• FIGURE 10-5 TIME-CODE OUTPUT INTERFACE

  131
• FIGURE 10-6 TIME-CODE TIME_CTR_RST INTERFACE

  131
• FIGURE 12-1 PLL LAYOUT RECOMMENDATIONS

  142
• FIGURE 13-1 RESET WAVEFORM

  146
• FIGURE 13-2 RESET WAVEFORM WITH DATA AND STROBE BOTH HIGH

  146
• FIGURE 13-3 GLITCHES ON DATA OR STROBE DURING RESET

  146
• FIGURE 13-4 SIMULTANEOUS TRANSITION OF DATA AND STROBE DURING RESET

  146
• FIGURE 13-5 LINK DISCONNECT WAVEFORMS

  147
• FIGURE 13-6 DATA AFTER PARITY ERROR ANOMALY

  148
• FIGURE 13-7 NO ERROR END OF PACKET INSERTED AFTER PARITY ERROR

  149
• TABLE 1-1 APPLICABLE DOCUMENTS

  15
• TABLE 1-2 REFERENCE DOCUMENTS

  15
• TABLE 5-1 GLOBAL SIGNALS

  32
• TABLE 5-2 DATA AND STROBE SPACEWIRE SIGNALS

  33
• TABLE 5-3 EXTERNAL PORT INTERFACE SIGNALS

  37
• TABLE 5-4 TIME-CODE SIGNALS

  39
• TABLE 5-5 LINK ERROR INDICATION SIGNALS

  41
• TABLE 5-6 RESET CONFIGURATION SIGNALS

  43
• TABLE 5-7 POWER, GROUND AND SPECIAL SIGNALS

  45
• TABLE 6-1 MULTIPLEXED STATUS PINS BIT ASSIGNMENT

  50
• TABLE 7-1 PACKET ADDRESS MAPPING

  52
• TABLE 7-2 PACKET PRIORITY MAPPING

  53
• TABLE 7-3 PACKET HEADER DELETION MAPPING

  54
• TABLE 7-4 SUPPORTED RMAP COMMAND CODES

  56
• TABLE 7-5 READ SINGLE ADDRESS CHARACTERISTICS

  57
• TABLE 7-6 READ SINGLE ADDRESS COMMAND PACKET FIELDS

  58
• TABLE 7-7 READ SINGLE ADDRESS REPLY PACKET FIELDS

  59
• TABLE 7-8 READ INCREMENTING ADDRESS CHARACTERISTICS

  61
• TABLE 7-9 READ INCREMENTING ADDRESS COMMAND PACKET FIELDS

  62
• TABLE 7-10 READ INCREMENTING ADDRESS REPLY PACKET FIELDS

  64
• TABLE 7-11 READ-MODIFY-WRITE COMMAND CHARACTERISTICS

  65
• TABLE 7-12 READ-MODIFY-WRITE COMMAND PACKET FIELDS

  67
• TABLE 7-13 READ-MODIFY-WRITE REPLY PACKET FIELDS

  69
• TABLE 7-14 WRITE COMMAND CHARACTERISTICS

  70
• TABLE 7-15 WRITE SINGLE ADDRESS COMMAND PACKET FIELDS

  71
• TABLE 7-16 WRITE SINGLE ADDRESS REPLY PACKET FIELDS

  73
• TABLE 7-17 CONFIGURATION PORT ERRORS SUMMARY

  74
• TABLE 7-18 SOURCE PATH ADDRESS REFERENCE TABLE

  77
• TABLE 8-1 SETTING SPACEWIRE TRANSMIT DATA RATE

  83
• TABLE 9-1 TYPES OF REGISTER WITHIN CONFIGURATION PORT

  104
• TABLE 9-2 CONFIGURATION REGISTER ADDRESSES

  105
• TABLE 9-3 GAR TABLE REGISTER DESCRIPTION

  107
• TABLE 9-4 CONFIGURATION PORT CONTROL/STATUS REGISTER FIELDS

  108
• TABLE 9-5 CONFIGURATION PORT CONTROL/STATUS REGISTER FIELDS

  110
• TABLE 9-6 SPACEWIRE PORT CONTROL/STATUS REGISTER FIELDS.

  113
• TABLE 9-7 EXTERNAL PORT CONTROL/STATUS FIELDS

  115
• TABLE 9-8 NETWORK DISCOVERY REGISTER FIELDS

  116
• TABLE 9-9 ROUTER IDENTITY REGISTER FIELD

  117
• TABLE 9-10 ROUTER CONTROL REGISTER FIELDS

  118
• TABLE 9-11 ERROR ACTIVE REGISTER FIELDS

  121
• TABLE 9-12 TIME-CODE REGISTER FIELDS

  122
• TABLE 9-13 DEVICE MANUFACTURER AND CHIP ID REGISTER FIELDS

  122
• TABLE 9-14 TIME-CODE ENABLE REGISTER FIELDS

  124
• TABLE 9-15 TRANSMIT CLOCK CONTROL REGISTER BITS

  126
• TABLE 9-16 DESTINATION KEY REGISTER

  127
• TABLE 10-1 CLOCK AND RESET TIMING PARAMETERS

  128
• TABLE 10-2 SERIAL SIGNAL TIMING PARAMETERS

  129
• TABLE 10-3 EXTERNAL PORT TIMING PARAMETERS

  130
• TABLE 10-4 TIME-CODE INTERFACE TIMING PARAMETERS

  131
• TABLE 10-5 STATUS MULTIPLEXER TIMING PARAMETERS

  132
• TABLE 10-6 SPACEWIRE ROUTER LATENCY AND JITTER MEASUREMENTS (BIT RATE = 200MBITS/S

  135
• TABLE 11-1 OPERATING CONDITIONS

  136
• TABLE 11-2 ABSOLUTE MAXIMUM RATINGS

  137
• TABLE 11-3 RELIABILTY INFORMATION

  137