ユーザーズマニュアル (UCS-CPU-E52450BC=)目次1 Overview131.1 Introduction131.1.1 Processor Feature Details141.1.2 Supported Technologies151.2 Interfaces151.2.1 System Memory Support151.2.2 PCI Express*161.2.3 Direct Media Interface Gen 2 (DMI2)181.2.4 Intel® QuickPath Interconnect (Intel® QPI)181.2.5 Platform Environment Control Interface (PECI)191.3 Power Management Support191.3.1 Processor Package and Core States191.3.2 System States Support191.3.3 Memory Controller191.3.4 PCI Express201.3.5 Intel QuickPath Interconnect201.4 Thermal Management Support201.5 Package Summary201.6 Terminology201.7 Related Documents231.8 State of Data242 Interfaces252.1 System Memory Interface252.1.1 System Memory Technology Support252.1.2 System Memory Timing Support252.2 PCI Express* Interface262.2.1 PCI Express* Architecture262.2.2 PCI Express* Configuration Mechanism272.3 DMI2/PCI Express* Interface282.3.1 DMI2 Error Flow282.3.2 Processor/PCH Compatibility Assumptions282.3.3 DMI2 Link Down282.4 Intel QuickPath Interconnect282.5 Platform Environment Control Interface (PECI)302.5.1 PECI Client Capabilities302.5.2 Client Command Suite312.5.3 Client Management692.5.4 Multi-Domain Commands742.5.5 Client Responses752.5.6 Originator Responses762.5.7 DTS Temperature Data763 Technologies793.1 Intel® Virtualization Technology (Intel® VT)793.1.1 Intel VT-x Objectives793.1.2 Intel VT-x Features803.1.3 Intel VT-d Objectives803.1.4 Intel Virtualization Technology Processor Extensions813.2 Security Technologies813.2.1 Intel® Trusted Execution Technology813.2.2 Intel Trusted Execution Technology – Server Extensions823.2.3 Intel® Advanced Encryption Standard Instructions (Intel® AES-NI)823.2.4 Execute Disable Bit833.3 Intel® Hyper-Threading Technology833.4 Intel® Turbo Boost Technology833.4.1 Intel® Turbo Boost Operating Frequency833.5 Enhanced Intel SpeedStep® Technology843.6 Intel® Intelligent Power Technology843.7 Intel® Advanced Vector Extensions (Intel® AVX)843.8 Intel® Dynamic Power Technology (Intel® DPT)854 Power Management874.1 ACPI States Supported874.1.1 System States874.1.2 Processor Package and Core States874.1.3 Integrated Memory Controller States884.1.4 DMI2/PCI Express Link States894.1.5 Intel QuickPath Interconnect States894.1.6 G, S, and C State Combinations894.2 Processor Core/Package Power Management904.2.1 Enhanced Intel SpeedStep® Technology904.2.2 Low-Power Idle States904.2.3 Requesting Low-Power Idle States914.2.4 Core C-states924.2.5 Package C-States944.2.6 Package C-State Power Specifications974.3 System Memory Power Management974.3.1 CKE Power-Down984.3.2 Self Refresh984.3.3 DRAM I/O Power Management994.4 DMI2/PCI Express* Power Management995 Thermal Management Specifications1015.1 Package Thermal Specifications1015.1.1 Thermal Specifications1015.1.2 TCASE and DTS Based Thermal Specifications1025.1.3 Processor Thermal Profiles1045.1.4 Embedded Server Processor Thermal Profiles1325.1.5 Thermal Metrology1375.2 Processor Core Thermal Features1385.2.1 Processor Temperature1385.2.2 Adaptive Thermal Monitor1385.2.3 On-Demand Mode1405.2.4 PROCHOT_N Signal1405.2.5 THERMTRIP_N Signal1415.2.6 Integrated Memory Controller (IMC) Thermal Features1416 Signal Descriptions1436.1 System Memory Interface Signals1436.2 PCI Express* Based Interface Signals1446.3 DMI2/PCI Express* Port 0 Signals1466.4 Intel QuickPath Interconnect Signals1466.5 PECI Signal1476.6 System Reference Clock Signals1476.7 JTAG and TAP Signals1476.8 Serial VID Interface (SVID) Signals1486.9 Processor Asynchronous Sideband and Miscellaneous Signals1486.10 Processor Power and Ground Supplies1507 Electrical Specifications1537.1 Processor Signaling1537.1.1 System Memory Interface Signal Groups1537.1.2 PCI Express* Signals1537.1.3 DMI2/PCI Express* Signals1537.1.4 Intel QuickPath Interconnect (Intel QPI)1537.1.5 Platform Environmental Control Interface (PECI)1547.1.6 System Reference Clocks (BCLK{0/1}_DP, BCLK{0/ 1}_DN)1547.1.7 JTAG and Test Access Port (TAP) Signals1557.1.8 Processor Sideband Signals1557.1.9 Power, Ground and Sense Signals1557.1.10 Reserved or Unused Signals1607.2 Signal Group Summary1607.3 Power-On Configuration (POC) Options1647.4 Fault Resilient Booting (FRB)1657.5 Mixing Processors1657.6 Flexible Motherboard Guidelines (FMB)1667.7 Absolute Maximum and Minimum Ratings1667.7.1 Storage Conditions Specifications1677.8 DC Specifications1687.8.1 Voltage and Current Specifications1697.8.2 Die Voltage Validation1757.8.3 Signal DC Specifications1767.9 Signal Quality1837.9.1 DDR3 Signal Quality Specifications1837.9.2 I/O Signal Quality Specifications1837.9.3 Intel QuickPath Interconnect Signal Quality Specifications1847.9.4 Input Reference Clock Signal Quality Specifications1847.9.5 Overshoot/Undershoot Tolerance1848 Processor Land Listing1878.1 Listing by Land Name1878.2 Listing by Land Number2129 Package Mechanical Specifications2379.1 Package Mechanical Drawing2379.2 Processor Component Keep-Out Zones2419.3 Package Loading Specifications2419.4 Package Handling Guidelines2419.5 Package Insertion Specifications2419.6 Processor Mass Specification2429.7 Processor Materials2429.8 Processor Markings24210 Boxed Processor Specifications24310.1 Introduction24310.1.1 Available Boxed Thermal Solution Configurations24310.1.2 Intel Thermal Solution STS200C (Passive/Active Combination Heat Sink Solution)24310.1.3 Intel Thermal Solution STS200P and STS200PNRW (Boxed 25.5 mm Tall Passive Heat Sink Solutions)24410.2 Mechanical Specifications24510.2.1 Boxed Processor Heat Sink Dimensions and Baseboard Keepout Zones24510.2.2 Boxed Processor Retention Mechanism and Heat Sink Support (ILM-RS)25410.3 Fan Power Supply [STS200C]25410.3.1 Boxed Processor Cooling Requirements25510.4 Boxed Processor Contents256サイズ： 2.77MBページ数： 258Language: Englishマニュアルを開く
