ユーザーズマニュアル目次Features1Configurations1Functional Description1Selection Guide1Logic Block Diagram (CY7C1511JV18)2Logic Block Diagram (CY7C1526JV18)2Logic Block Diagram (CY7C1513JV18)3Logic Block Diagram (CY7C1515JV18)3Pin Configuration4165-Ball FBGA (15 x 17 x 1.4 mm) Pinout4Pin Definitions6Functional Overview8Read Operations8Write Operations8Byte Write Operations8Single Clock Mode8Concurrent Transactions9Depth Expansion9Programmable Impedance9Echo Clocks9DLL9Application Example10Truth Table10Write Cycle Descriptions11Write Cycle Descriptions11Write Cycle Descriptions12IEEE 1149.1 Serial Boundary Scan (JTAG)13Disabling the JTAG Feature13Test Access Port-Test Clock13Test Mode Select (TMS)13Test Data-In (TDI)13Test Data-Out (TDO)13Performing a TAP Reset13TAP Registers13Instruction Register13Bypass Register13Boundary Scan Register13Identification (ID) Register13TAP Instruction Set13IDCODE14SAMPLE Z14SAMPLE/PRELOAD14BYPASS14EXTEST14EXTEST OUTPUT BUS TRI-STATE14Reserved14TAP Controller State Diagram15TAP Controller Block Diagram16TAP Electrical Characteristics16TAP AC Switching Characteristics17TAP Timing and Test Conditions17Identification Register Definitions18Scan Register Sizes18Instruction Codes18Boundary Scan Order19Power Up Sequence in QDR-II SRAM20Power Up Sequence20DLL Constraints20Power Up Waveforms20Maximum Ratings21Operating Range21Electrical Characteristics21DC Electrical Characteristics21AC Electrical Characteristics21Capacitance22Thermal Resistance22AC Test Loads and Waveforms22Switching Characteristics23Switching Waveforms24Ordering Information25Package Diagram26Document History Page27サイズ: 666KBページ数: 27Language: Englishマニュアルを開く