Fujitsu CM71-00101-5E マニュアル

目次

• CHAPTER 1 FR FAMILY OVERVIEW

  25
  • 1.1 Features of the FR Family CPU Core

    26
  • 1.2 Sample Configuration of an FR Family Device

    27
  • 1.3 Sample Configuration of the FR Family CPU

    28
• CHAPTER 2 MEMORY ARCHITECTURE

  29
  • 2.1 FR Family Memory Space

    30
    • 2.1.1 Direct Address Area

      31
    • 2.1.2 Vector Table Area

      32
  • 2.2 Bit Order and Byte Order

    34
  • 2.3 Word Alignment

    35
• CHAPTER 3 REGISTER DESCRIPTIONS

  37
  • 3.1 FR Family Register Configuration

    38
  • 3.2 General-purpose Registers

    39
  • 3.3 Dedicated Registers

    41
    • 3.3.1 Program Counter (PC)

      42
    • 3.3.2 Program Status (PS)

      43
    • 3.3.3 Table Base Register (TBR)

      47
    • 3.3.4 Return Pointer (RP)

      49
    • 3.3.5 System Stack Pointer (SSP), User Stack Pointer (USP)

      51
    • 3.3.6 Multiplication/Division Register (MD)

      53
• CHAPTER 4 RESET AND "EIT" PROCESSING

  55
  • 4.1 Reset Processing

    57
  • 4.2 Basic Operations in "EIT" Processing

    58
  • 4.3 Interrupts

    61
    • 4.3.1 User Interrupts

      62
    • 4.3.2 Non-maskable Interrupts (NMI)

      64
  • 4.4 Exception Processing

    66
    • 4.4.1 Undefined Instruction Exceptions

      67
  • 4.5 Traps

    68
    • 4.5.1 "INT" Instructions

      69
    • 4.5.2 "INTE" Instruction

      70
    • 4.5.3 Step Trace Traps

      71
    • 4.5.4 Coprocessor Not Found Traps

      72
    • 4.5.5 Coprocessor Error Trap

      73
  • 4.6 Priority Levels

    75
• CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU

  77
  • 5.1 Pipeline Operation

    78
  • 5.2 Pipeline Operation and Interrupt Processing

    79
  • 5.3 Register Hazards

    80
  • 5.4 Delayed Branching Processing

    82
    • 5.4.1 Processing Non-delayed Branching Instructions

      84
    • 5.4.2 Processing Delayed Branching Instructions

      85
• CHAPTER 6 INSTRUCTION OVERVIEW

  87
  • 6.1 Instruction Formats

    88
  • 6.2 Instruction Notation Formats

    90
• CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS

  91
  • 7.1 ADD (Add Word Data of Source Register to Destination Register)

    96
  • 7.2 ADD (Add 4-bit Immediate Data to Destination Register)

    97
  • 7.3 ADD2 (Add 4-bit Immediate Data to Destination Register)

    98
  • 7.4 ADDC (Add Word Data of Source Register and Carry Bit to Destination Register)

    99
  • 7.5 ADDN (Add Word Data of Source Register to Destination Register)

    100
  • 7.6 ADDN (Add Immediate Data to Destination Register)

    101
  • 7.7 ADDN2 (Add Immediate Data to Destination Register)

    102
  • 7.8 SUB (Subtract Word Data in Source Register from Destination Register)

    103
  • 7.9 SUBC (Subtract Word Data in Source Register and Carry Bit from Destination Register)

    104
  • 7.10 SUBN (Subtract Word Data in Source Register from Destination Register)

    105
  • 7.11 CMP (Compare Word Data in Source Register and Destination Register)

    106
  • 7.12 CMP (Compare Immediate Data of Source Register and Destination Register)

    107
  • 7.13 CMP2 (Compare Immediate Data and Destination Register)

    108
  • 7.14 AND (And Word Data of Source Register to Destination Register)

    109
  • 7.15 AND (And Word Data of Source Register to Data in Memory)

    110
  • 7.16 ANDH (And Half-word Data of Source Register to Data in Memory)

    112
  • 7.17 ANDB (And Byte Data of Source Register to Data in Memory)

    114
  • 7.18 OR (Or Word Data of Source Register to Destination Register)

    116
  • 7.19 OR (Or Word Data of Source Register to Data in Memory)

    117
  • 7.20 ORH (Or Half-word Data of Source Register to Data in Memory)

    119
  • 7.21 ORB (Or Byte Data of Source Register to Data in Memory)

    121
  • 7.22 EOR (Exclusive Or Word Data of Source Register to Destination Register)

    123
  • 7.23 EOR (Exclusive Or Word Data of Source Register to Data in Memory)

    124
  • 7.24 EORH (Exclusive Or Half-word Data of Source Register to Data in Memory)

    126
  • 7.25 EORB (Exclusive Or Byte Data of Source Register to Data in Memory)

    128
  • 7.26 BANDL (And 4-bit Immediate Data to Lower 4 Bits of Byte Data in Memory)

    130
  • 7.27 BANDH (And 4-bit Immediate Data to Higher 4 Bits of Byte Data in Memory)

    132
  • 7.28 BORL (Or 4-bit Immediate Data to Lower 4 Bits of Byte Data in Memory)

    134
  • 7.29 BORH (Or 4-bit Immediate Data to Higher 4 Bits of Byte Data in Memory)

    136
  • 7.30 BEORL (Eor 4-bit Immediate Data to Lower 4 Bits of Byte Data in Memory)

    138
  • 7.31 BEORH (Eor 4-bit Immediate Data to Higher 4 Bits of Byte Data in Memory)

    140
  • 7.32 BTSTL (Test Lower 4 Bits of Byte Data in Memory)

    142
  • 7.33 BTSTH (Test Higher 4 Bits of Byte Data in Memory)

    143
  • 7.34 MUL (Multiply Word Data)

    144
  • 7.35 MULU (Multiply Unsigned Word Data)

    146
  • 7.36 MULH (Multiply Half-word Data)

    148
  • 7.37 MULUH (Multiply Unsigned Half-word Data)

    150
  • 7.38 DIV0S (Initial Setting Up for Signed Division)

    152
  • 7.39 DIV0U (Initial Setting Up for Unsigned Division)

    154
  • 7.40 DIV1 (Main Process of Division)

    156
  • 7.41 DIV2 (Correction when Remainder is 0)

    158
  • 7.42 DIV3 (Correction when Remainder is 0)

    160
  • 7.43 DIV4S (Correction Answer for Signed Division)

    161
  • 7.44 LSL (Logical Shift to the Left Direction)

    162
  • 7.45 LSL (Logical Shift to the Left Direction)

    163
  • 7.46 LSL2 (Logical Shift to the Left Direction)

    164
  • 7.47 LSR (Logical Shift to the Right Direction)

    165
  • 7.48 LSR (Logical Shift to the Right Direction)

    166
  • 7.49 LSR2 (Logical Shift to the Right Direction)

    167
  • 7.50 ASR (Arithmetic Shift to the Right Direction)

    168
  • 7.51 ASR (Arithmetic Shift to the Right Direction)

    169
  • 7.52 ASR2 (Arithmetic Shift to the Right Direction)

    170
  • 7.53 LDI:32 (Load Immediate 32-bit Data to Destination Register)

    171
  • 7.54 LDI:20 (Load Immediate 20-bit Data to Destination Register)

    172
  • 7.55 LDI:8 (Load Immediate 8-bit Data to Destination Register)

    173
  • 7.56 LD (Load Word Data in Memory to Register)

    174
  • 7.57 LD (Load Word Data in Memory to Register)

    175
  • 7.58 LD (Load Word Data in Memory to Register)

    176
  • 7.59 LD (Load Word Data in Memory to Register)

    177
  • 7.60 LD (Load Word Data in Memory to Register)

    178
  • 7.61 LD (Load Word Data in Memory to Register)

    179
  • 7.62 LD (Load Word Data in Memory to Program Status Register)

    181
  • 7.63 LDUH (Load Half-word Data in Memory to Register)

    183
  • 7.64 LDUH (Load Half-word Data in Memory to Register)

    184
  • 7.65 LDUH (Load Half-word Data in Memory to Register)

    185
  • 7.66 LDUB (Load Byte Data in Memory to Register)

    186
  • 7.67 LDUB (Load Byte Data in Memory to Register)

    187
  • 7.68 LDUB (Load Byte Data in Memory to Register)

    188
  • 7.69 ST (Store Word Data in Register to Memory)

    189
  • 7.70 ST (Store Word Data in Register to Memory)

    190
  • 7.71 ST (Store Word Data in Register to Memory)

    191
  • 7.72 ST (Store Word Data in Register to Memory)

    192
  • 7.73 ST (Store Word Data in Register to Memory)

    193
  • 7.74 ST (Store Word Data in Register to Memory)

    194
  • 7.75 ST (Store Word Data in Program Status Register to Memory)

    195
  • 7.76 STH (Store Half-word Data in Register to Memory)

    196
  • 7.77 STH (Store Half-word Data in Register to Memory)

    197
  • 7.78 STH (Store Half-word Data in Register to Memory)

    198
  • 7.79 STB (Store Byte Data in Register to Memory)

    199
  • 7.80 STB (Store Byte Data in Register to Memory)

    200
  • 7.81 STB (Store Byte Data in Register to Memory)

    201
  • 7.82 MOV (Move Word Data in Source Register to Destination Register)

    202
  • 7.83 MOV (Move Word Data in Source Register to Destination Register)

    203
  • 7.84 MOV (Move Word Data in Program Status Register to Destination Register)

    204
  • 7.85 MOV (Move Word Data in Source Register to Destination Register)

    205
  • 7.86 MOV (Move Word Data in Source Register to Program Status Register)

    206
  • 7.87 JMP (Jump)

    208
  • 7.88 CALL (Call Subroutine)

    209
  • 7.89 CALL (Call Subroutine)

    210
  • 7.90 RET (Return from Subroutine)

    211
  • 7.91 INT (Software Interrupt)

    212
  • 7.92 INTE (Software Interrupt for Emulator)

    214
  • 7.93 RETI (Return from Interrupt)

    216
  • 7.94 Bcc (Branch Relative if Condition Satisfied)

    218
  • 7.95 JMP:D (Jump)

    220
  • 7.96 CALL:D (Call Subroutine)

    221
  • 7.97 CALL:D (Call Subroutine)

    223
  • 7.98 RET:D (Return from Subroutine)

    225
  • 7.99 Bcc:D (Branch Relative if Condition Satisfied)

    227
  • 7.100 DMOV (Move Word Data from Direct Address to Register)

    229
  • 7.101 DMOV (Move Word Data from Register to Direct Address)

    230
  • 7.102 DMOV (Move Word Data from Direct Address to Post Increment Register Indirect Address)

    231
  • 7.103 DMOV (Move Word Data from Post Increment Register Indirect Address to Direct Address)

    233
  • 7.104 DMOV (Move Word Data from Direct Address to Pre-decrement Register Indirect Address)

    235
  • 7.105 DMOV (Move Word Data from Post Increment Register Indirect Address to Direct Address)

    237
  • 7.106 DMOVH (Move Half-word Data from Direct Address to Register)

    239
  • 7.107 DMOVH (Move Half-word Data from Register to Direct Address)

    240
  • 7.108 DMOVH (Move Half-word Data from Direct Address to Post Increment Register Indirect Address)

    241
  • 7.109 DMOVH (Move Half-word Data from Post Increment Register Indirect Address to Direct Address)

    243
  • 7.110 DMOVB (Move Byte Data from Direct Address to Register)

    245
  • 7.111 DMOVB (Move Byte Data from Register to Direct Address)

    246
  • 7.112 DMOVB (Move Byte Data from Direct Address to Post Increment Register Indirect Address)

    247
  • 7.113 DMOVB (Move Byte Data from Post Increment Register Indirect Address to Direct Address)

    249
  • 7.114 LDRES (Load Word Data in Memory to Resource)

    251
  • 7.115 STRES (Store Word Data in Resource to Memory)

    252
  • 7.116 COPOP (Coprocessor Operation)

    253
  • 7.117 COPLD (Load 32-bit Data from Register to Coprocessor Register)

    255
  • 7.118 COPST (Store 32-bit Data from Coprocessor Register to Register)

    257
  • 7.119 COPSV (Save 32-bit Data from Coprocessor Register to Register)

    259
  • 7.120 NOP (No Operation)

    261
  • 7.121 ANDCCR (And Condition Code Register and Immediate Data)

    262
  • 7.122 ORCCR (Or Condition Code Register and Immediate Data)

    263
  • 7.123 STILM (Set Immediate Data to Interrupt Level Mask Register)

    264
  • 7.124 ADDSP (Add Stack Pointer and Immediate Data)

    265
  • 7.125 EXTSB (Sign Extend from Byte Data to Word Data)

    266
  • 7.126 EXTUB (Unsign Extend from Byte Data to Word Data)

    267
  • 7.127 EXTSH (Sign Extend from Byte Data to Word Data)

    268
  • 7.128 EXTUH (Unsigned Extend from Byte Data to Word Data)

    269
  • 7.129 LDM0 (Load Multiple Registers)

    270
  • 7.130 LDM1 (Load Multiple Registers)

    272
  • 7.131 STM0 (Store Multiple Registers)

    274
  • 7.132 STM1 (Store Multiple Registers)

    276
  • 7.133 ENTER (Enter Function)

    278
  • 7.134 LEAVE (Leave Function)

    280
  • 7.135 XCHB (Exchange Byte Data)

    282
• APPENDIX

  285
  • APPENDIX A Instruction Lists

    286
    • A.1 Symbols Used in Instruction Lists

      287
    • A.2 Instruction Lists

      289
  • APPENDIX B Instruction Maps

    298
    • B.1 Instruction Map

      299
    • B.2 "E" Format

      300
• INDEX

  301
  • A

    302
  • B

    302
  • C

    303
  • D

    303
  • E

    305
  • F

    305
  • G

    305
  • H

    306
  • I

    306
  • J

    307
  • L

    307
  • M

    308
  • N

    309
  • O

    309
  • P

    309
  • R

    309
  • S

    310
  • T

    312
  • U

    312
  • V

    312
  • W

    312
  • X

    312