ユーザーズマニュアル目次Description3Features3Ordering Information3Key Parameters4Speed Grade4Address Table4Pin Descriptions5Input/Output Functional Descriptions6Pin Assignments8Registering Clock Driver Specifications10Capacitance Values10Input & Output Timing Requirements10On DIMM Thermal Sensor11Connection of Thermal Sensor11Temperature-to-Digital Conversion Performance11Functional Block Diagram124GB, 512Mx72 Module(1Rank of x8)128GB, 1Gx72 Module(1Rank of x4) - page1138GB, 1Gx72 Module(1Rank of x4) - page2148GB, 1Gx72 Module(2Rank of x8) - page1158GB, 1Gx72(2Rank of x8) - page21616GB, 2Gx72 Module(2Rank of x4) - page11716GB, 2Gx72 Module(2Rank of x4) - page21816GB, 2Gx72 Module(2Rank of x4) - page31932GB, 4Gx72 Module(4Rank of x4) - page12032GB, 4Gx72 Module(4Rank of x4) - page22132GB, 4Gx72 Module(4Rank of x4) - page32232GB, 4Gx72 Module(4Rank of x4) - page42332GB, 4Gx72 Module(4Rank of x4) - page524Absolute Maximum Ratings25Absolute Maximum DC Ratings25DRAM Component Operating Temperature Range25AC & DC Operating Conditions26Recommended DC Operating Conditions26AC & DC Input Measurement Levels27AC and DC Input Levels for Single-Ended Command and Address Signals27AC and DC Input Levels for Single-Ended Signals28Vref Tolerances29AC and DC Logic Input Levels for Differential Signals30Differential signal definition30Differential swing requirements for clock (CK - CK) and strobe (DQS-DQS)31note : Rising input differential signal shall become equal to or greater than VIHdiff(ac) level and Falling input differential signal shall become equal to or less than VIL(ac) level.31Single-ended requirements for differential signals32Differential Input Cross Point Voltage34Slew Rate Definitions for Single-Ended Input Signals35Slew Rate Definitions for Differential Input Signals35AC & DC Output Measurement Levels36Single Ended AC and DC Output Levels36Differential AC and DC Output Levels36Single Ended Output Slew Rate37Differential Output Slew Rate38Reference Load for AC Timing and Output Slew Rate39Overshoot and Undershoot Specifications40Address and Control Overshoot and Undershoot Specifications40Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications41Refresh parameters by device density42Standard Speed Bins43DDR3-800 Speed Bins43DDR3-1066 Speed Bins44DDR3-1333 Speed Bins45DDR3-1600 Speed Bins46DDR3-1866 Speed Bins47Speed Bin Table Notes48Environmental Parameters49IDD and IDDQ Specification Parameters and Test Conditions50IDD Specifications (Tcase: 0 to 95oC)624GB, 512M x 72 R-DIMM: HMT451R7AFR8C628GB, 1G x 72 R-DIMM: HMT41GR7AFR4C628GB, 1G x 72 R-DIMM: HMT41GR7AFR8C6316GB, 2G x 72 R-DIMM: HMT42GR7AFR4C6332GB, 4G x 72 R-DIMM: HMT84GR7AMR4C64Module Dimensions65512Mx72 - HMT451R7AFR8C651Gx72 - HMT41GR7AFR4C661Gx72 - HMT41GR7AFR8C672Gx72 - HMT42GR7AFR4C682Gx72 - HMT42GR7AFR4C - Heat Spreader694Gx72 - HMT84GR7AMR4C704Gx72 - HMT84GR7AMR4C - Heat Spreader71サイズ： 1.24MBページ数： 71Language: Englishマニュアルを開く
