Intel 4 マニュアル

目次

• 1.0 Introduction

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  • 1.1 Terminology

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    • 1.1.1 Processor Packaging Terminology

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  • 1.2 References

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    • Table 1. References

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• 2.0 Electrical Specifications

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  • 2.1 System Bus and GTLREF

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  • 2.2 Power and Ground Pins

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  • 2.3 Decoupling Guidelines

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    • 2.3.1 VCC Decoupling

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    • 2.3.2 System Bus AGTL+ Decoupling

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    • 2.3.3 System Bus Clock (BCLK[1:0]) and Processor Clocking

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  • 2.4 Voltage Identification

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    • Table 2. Voltage Identification Definition

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    • 2.4.1 Phase Lock Loop (PLL) Power and Filter

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      • Figure 1. Typical VCCIOPLL, VCCA and VSSA Power Distribution

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      • Figure 2. Phase Lock Loop (PLL) Filter Requirements

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  • 2.5 Reserved, Unused Pins, and TESTHI[10:0]

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  • 2.6 System Bus Signal Groups

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    • Table 3. System Bus Pin Groups (Page 1 of 2)

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  • 2.7 Asynchronous GTL+ Signals

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  • 2.8 Test Access Port (TAP) Connection

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  • 2.9 Maximum Ratings

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    • Table 4. Processor DC Absolute Maximum Ratings

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  • 2.10 Processor DC Specifications

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    • Table 5. Voltage and Current Specifications

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    • Table 6. System Bus Differential BCLK Specifications

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    • Table 7. AGTL+ Signal Group DC Specifications

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    • Table 8. Asynchronous GTL+ and TAP Signal Group DC Specifications

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  • 2.11 AGTL+ System Bus Specifications

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    • Table 9. AGTL+ Bus Voltage Definitions

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  • 2.12 System Bus AC Specifications

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    • Table 10. System Bus Differential Clock Specifications

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    • Table 11. System Bus Common Clock AC Specifications

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    • Table 12. System Bus Source Synch AC Specifications AGTL+ Signal Group

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    • Table 13. Asynchronous GTL+ Signals AC Specifications

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    • Table 14. System Bus AC Specifications (Reset Conditions)

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    • Table 15. TAP Signals AC Specifications

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  • 2.13 Processor AC Timing Waveforms

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    • Figure 3. AC Test Circuit

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    • Figure 4. TCK Clock Waveform

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    • Figure 5. Differential Clock Waveform

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    • Figure 6. System Bus Common Clock Valid Delay Timings

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    • Figure 7. System Bus Reset and Configuration Timings

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    • Figure 8. Source Synchronous 2X (Address) Timings

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    • Figure 9. Source Synchronous 4X Timings

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    • Figure 10. Power-On Reset and Configuration Timings

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    • Figure 11. Test Reset Timings

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• 3.0 System Bus Signal Quality Specifications

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  • 3.1 BCLK Signal Quality Specifications and Measurement Guidelines

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    • Table 16. BCLK Signal Quality Specifications

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    • Figure 12. BCLK[1:0] Signal Integrity Waveform

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  • 3.2 System Bus Signal Quality Specifications and Measurement Guidelines

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    • Table 17. Ringback Specifications for AGTL+, Asynchronous GTL+, and TAP Signal Groups

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    • Figure 13. Low-to-High System Bus Receiver Ringback Tolerance

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    • Figure 14. High-to-Low System Bus Receiver Ringback Tolerance

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  • 3.3 System Bus Signal Quality Specifications and Measurement Guidelines

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    • 3.3.1 Overshoot/Undershoot Guidelines

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    • 3.3.2 Overshoot/Undershoot Magnitude

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    • 3.3.3 Overshoot/Undershoot Pulse Duration

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    • 3.3.4 Activity Factor

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    • 3.3.5 Reading Overshoot/Undershoot Specification Tables

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    • 3.3.6 Determining if a System Meets the Over/Undershoot Specifications

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      • Table 18. Source Synchronous (400MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance (1.7V Pro...

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      • Table 19. Source Synchronous (200MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance (1.7V Pro...

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      • Table 20. Common Clock (100MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance (1.7V Processors)

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      • Table 21. Asynchronous GTL+ and TAP Signal Groups Overshoot/Undershoot Tolerance (1.7V Processors)

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      • Table 22. Source Synchronous (400MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance (1.75V Pr...

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      • Table 23. Source Synchronous (200MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance (1.75V Pr...

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      • Table 24. Common Clock (100MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance (1.75V Processors)

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      • Table 25. Asynchronous GTL+ and TAP Signal Groups Overshoot/Undershoot Tolerance (1.75V Processors)

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      • Figure 15. Maximum Acceptable Overshoot/Undershoot Waveform

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• 4.0 Package Mechanical Specifications

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  • Figure 16. Exploded View of Processor Components on a System Board

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  • Figure 17. Processor Package

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  • Table 26. Description Table for Processor Dimensions

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  • Figure 18. Processor Cross-Section and Keep-in

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  • Figure 19. Processor Pin Detail

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  • Figure 20. IHS Flatness Specification

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  • 4.1 Package Load Specifications

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    • Table 27. Package Dynamic and Static Load Specifications

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  • 4.2 Processor Insertion Specifications

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  • 4.3 Processor Mass Specifications

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    • Table 28. Processor Mass

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  • 4.4 Processor Materials

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    • Table 29. Processor Material Properties

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  • 4.5 Processor Markings

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    • Figure 21. Processor Markings

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  • 4.6 Processor Pin-Out Coordinates

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    • Figure 22. Processor Pinout Diagram - Bottom View

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    • Table 30. Pin Listing by Pin Name

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    • Table 31. Pin Listing by Pin Number

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• 5.0 Pin Listing and Signal Definitions

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  • 5.1 Processor Pin Assignments

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    • 5.1.1 Pin Listing by Pin Name

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    • 5.1.2 Pin Listing by Pin Number

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  • 5.2 Alphabetical Signals Reference

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    • Table 32. Signal Description (Page 1 of 8)

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• 6.0 Thermal Specifications and Design Considerations

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  • Figure 23. Example Thermal Solution (Not to scale)

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  • 6.1 Thermal Specifications

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    • Table 33. Processor Thermal Design Power

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  • 6.2 Thermal Analysis

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    • 6.2.1 Measurements For Thermal Specifications

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      • 6.2.1.1 Processor Case Temperature Measurement

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        • Figure 24. Guideline Locations for Case Temperature (TCASE) Thermocouple Placement

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        • Figure 25. Technique for Measuring with 0 Degree Angle Attachment

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        • Figure 26. Technique for Measuring with 90 Degree Angle Attachment

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• 7.0 Features

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  • 7.1 Power-On Configuration Options

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    • Table 34. Power-On Configuration Option Pins

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  • 7.2 Clock Control and Low Power States

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    • 7.2.1 Normal State—State 1

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    • 7.2.2 AutoHALT Powerdown State—State 2

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      • Figure 27. Stop Clock State Machine

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    • 7.2.3 Stop-Grant State—State 3

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    • 7.2.4 HALT/Grant Snoop State—State 4

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    • 7.2.5 Sleep State—State 5

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    • 7.2.6 Deep Sleep State—State 6

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  • 7.3 Thermal Monitor

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    • 7.3.1 Thermal Diode

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      • Table 35. Thermal Diode Parameters

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      • Table 36. Thermal Diode Interface

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• 8.0 Boxed Processor Specifications

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  • 8.1 Introduction

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    • Figure 28. Mechanical Representation of the Boxed Pentium 4 Processor

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  • 8.2 Mechanical Specifications

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    • 8.2.1 Boxed Processor Fan Heatsink Dimensions

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      • Figure 29. Side View Space Requirements for the Boxed Processor

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      • Figure 30. Top View Space Requirements for the Boxed Processor

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    • 8.2.2 Boxed Processor Fan Heatsink Weight

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    • 8.2.3 Boxed Processor Retention Mechanism and Fan Heatsink Supports

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  • 8.3 Boxed Processor Requirements

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    • 8.3.1 Fan Heatsink Power Supply

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      • Figure 31. Boxed Processor Fan Heatsink Power Cable Connector Description

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      • Table 37. Fan Heatsink Power and Signal Specifications

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      • Figure 32. Acceptable System Board Power Header Placement Relative to Processor Socket

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  • 8.4 Thermal Specifications

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    • 8.4.1 Boxed Processor Cooling Requirements

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      • Figure 33. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 1 view)

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      • Figure 34. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 2 view)

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    • 8.4.2 Variable Speed Fan

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      • Figure 35. Boxed Processor Fan Heatsink Set Points

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      • Table 38. Boxed Processor Fan Heatsink Set Points

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• 9.0 Debug Tools Specifications

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  • 9.1 Logic Analyzer Interface (LAI)

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    • 9.1.1 Mechanical Considerations

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    • 9.1.2 Electrical Considerations

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