ユーザーズマニュアル目次Title Page1Contents3Revision History12Introduction13About This Design Guide13Reference Documents14System Overview15Chipset Components16Bandwidth Summary17System Configuration18Platform Initiatives20Direct Rambus RAM (RDRAM*)20Streaming SIMD Extensions20AGP 2.0.20Hub Interface20Integrated LAN Controller21Ultra ATA/100 Support21Expanded USB Support21Manageability21AC’9723Low-Pin-Count (LPC) Interface25Layout/Routing Guidelines27General Recommendations27Component Quadrant Layout27Intel® 820E Chipset Component Placement29Core Chipset Routing Recommendations30Source-Synchronous Strobing32Differential Clocking/Strobing33Direct RDRAM* Interface33Stack-Up34Direct RDRAM* Layout Guidelines34RSL Routing35RSL Termination38Direct RDRAM* Ground Plane Reference39Direct RDRAM* Connector Compensation41Direct RDRAM* Channel Connector Compensation Enhancement Recommendation47RSL Signal Layer Alternation49Length Matching Methods50Via Compensation52Length Matching and Via Compensation Example52Direct RDRAM* Reference Voltage54High-Speed CMOS Routing54SIO Routing55Suspend-to-RAM Shunt Transistor56Direct RDRAM* Clock Routing57Direct RDRAM* Design Checklist57AGP 2.060AGP Interface Signal Groups601× Timing Domain Routing Guidelines622×/4× Timing Domain Routing Guidelines62AGP 2.0 Routing Summary64AGP Clock Routing65General AGP Routing Guidelines65Recommendations65VDDQ Generation and TYPEDET#66VREF Generation for AGP 2.0 (2× and 4×)68Compensation70AGP Pull-Ups70AGP Signal Voltage Tolerance List71Motherboard / Add-in Card Interoperability71AGP Universal Retention Mechanism (RM)72Hub Interface748-Bit Hub Interface Routing Guidelines758-Bit Hub Interface Data Signals758-Bit Hub Interface Strobe Signals758-Bit Hub Interface HUBREF Generation/Distribution758-Bit Hub Interface Compensation778-Bit Hub Interface Decoupling Guidelines77System Bus Design – Pentium® III Processor for the Intel® PGA370 Socket Layout Guidelines77System Bus Ground Plane Reference78Additional Host Bus Guidelines78IDE Interface79Cable Detection for Ultra ATA/66 and Ultra ATA/10080Combination Host-Side/Device-Side Cable Detection80Device-Side Cable Detection82Primary IDE Connector Requirements83Secondary IDE Connector Requirements84AC’9785AC’97 Audio Codec Detect Circuit and Configuration Options86Communication and Networking Riser (CNR)90AC’97 Routing91Motherboard Implementation92USB92Using Native USB Interface92Disabling the Native USB Interface of ICH293ISA Support93I/O APIC Design Recommendation94SMBus/SMLink Interface94PCI96RTC96RTC Crystal97External Capacitors97RTC Layout Considerations98RTC External Battery Connection98RTC External RTCRST Circuit99RTC Routing Guidelines100VBIAS DC Voltage and Noise Measurements100RTC-Well Input Strap Requirements100SPKR Pin Consideration100ICH2 PIRQ Routing101LAN Layout Guidelines102ICH2 – LAN Interconnect Guidelines103Bus Topologies104Point-to-Point Interconnect104LOM/CNR Interconnect104Signal Routing and Layout105Crosstalk Consideration106Impedances106Line Termination106General LAN Routing Guidelines and Considerations107General Trace Routing Considerations107Trace Geometry and Length108Signal Isolation108Power and Ground Connections108General Power and Ground Plane Considerations1084-Layer Board Design110Intel® 82562EH Home/PNA* Guidelines112Power and Ground Connections112Guidelines for Intel® 82562EH Component Placement112Crystals and Oscillators112Phoneline HPNA Termination113Critical Dimensions114Distance from Magnetics Module to Line RJ11114Distance from Intel® 82562EH Component to Magnetics Module114Distance from LPF to Phone RJ11115Intel® 82562ET / Intel® 82562EM Component Guidelines115Guidelines for Intel® 82562ET / Intel® 82562EM Component Placement115Crystals and Oscillators116Intel® 82562ET / Intel® 82562EM Component Termination Resistors116Critical Dimensions116Distance from Magnetics Module to RJ45117Distance from the Intel® 82562ET Component to the Magnetics Module118Reducing Circuit Inductance118Terminating Unused Connections118Termination Plane Capacitance118Intel® 82562ET/EM Disable Guidelines119Intel® 82562ET and Intel® 82562EH Components’ Dual-Footprint Guidelines120ICH2 Decoupling Recommendations122FWH Flash BIOS Guidelines124In-Circuit FWH Flash BIOS Programming124FWH Flash BIOS VPP Design Guidelines124ICH2 Design Checklist125ICH2 Layout Checklist134Advanced System Bus Design139Terminology and Definitions139Initial Timing Analysis142Determine the Desired General Topology, Layout, and Routing145Pre-Layout Simulation145Methodology145Sensitivity Analysis145Monte Carlo Analysis146Simulation Criteria146Place and Route Board147Estimate Component-to-Component Spacing for AGTL+ Signals147Layout and Route Board147Host Clock Routing148APIC Data Bus Routing148Post-Layout Simulation149Intersymbol Interference149Crosstalk Analysis150Monte Carlo Analysis150Validation150Measurements150Flight Time Simulation150Flight Time Hardware Validation151Theory152AGTL+152Timing Requirements152Crosstalk Theory153Potential Termination Crosstalk Problems154More Details and Insight155Textbook Timing Equations155Effective Impedance and Tolerance/Variation156Power/Reference Planes, PCB Stack-Up, and High-Frequency Decoupling156Power Distribution156Reference Planes and PCB Stack-Up157High-Frequency Decoupling159Clock Routing160Definitions of Flight Time Measurements/Corrections and Signal Quality160VREF Guard Band161Ringback Levels161Overdrive Region161Flight Time Definition and Measurement162Conclusion162Clocking163Clock Generation163Component Placement and Interconnection Layout Requirements16814.318 MHz Crystal to CK133168CK133 to DRCG168MCH to DRCG169DRCG-to-RDRAM Channel170Trace Length170DRCG Impedance Matching Circuit172DRCG Layout Example173AGP Clock Routing Guidelines173Clock Routing Guidelines for Intel® PGA370 Designs173Series Termination Resistors for CK133 Clock Outputs173Unused Outputs174Decoupling Recommendation for CK133 and DRCG174DRCG Frequency Selection and the DRCG+175DRCG Frequency Selection Table and Jitter Specification175DRCG+ Frequency Selection Schematic176System Manufacturing177Stack-Up Requirement177PCB Materials177Design Process178Test Coupon Design Guidelines178Recommended Stack-Up179Inner-Layer Routing179Impedance Calculation Tools180Testing Board Impedance181Board Impedance/Stack-up Summary181System Design Considerations183Power Delivery183Terminology and Definitions183ICH2 1.8 V / 3.3 V Power Sequencing188Excessive Power Consumption by 64/72-Mbit RDRAM190Option 1: Reduce the Clock Frequency During Initialization190Option 2: Increase the Current Capability of the 2.5 V Voltage Regulator191ICH2 Power Plane Split192Thermal Design Power193Glue Chip 3 (Intel® 820E Chipset Glue Chip)193Appendix A: Reference Design Schematics (Uniprocessor)195サイズ： 2.87MBページ数： 239Language: Englishマニュアルを開く
