ユーザーズマニュアル目次Introduction 1151.1 Scope151.2 Overview151.3 Ethernet Controller Features161.3.1 PCI Features161.3.2 CSA Features (82547GI/EI Only)161.3.3 Network Side Features161.3.4 Host Offloading Features171.3.5 Additional Performance Features181.3.6 Manageability Features (Not Applicable to the 82544GC/EI or 82541ER)191.3.7 Additional Ethernet Controller Features191.3.8 Technology Features191.4 Conventions201.4.1 Register and Bit References201.4.2 Byte and Bit Designations201.5 Related Documents201.6 Memory Alignment Terminology20Architectural Overview 2212.1 Introduction212.2 External Architecture222.3 Microarchitecture242.3.1 PCI/PCI-X Core Interface242.3.2 82547GI/EI CSA Interface252.3.3 DMA Engine and Data FIFO252.3.4 10/100/1000 Mb/s Receive and Transmit MAC Blocks262.3.5 MII/GMII/TBI/Internal SerDes Interface Block262.3.6 10/100/1000 Ethernet Transceiver (PHY)272.3.7 EEPROM Interface272.3.8 FLASH Memory Interface282.4 DMA Addressing282.5 Ethernet Addressing292.6 Interrupts302.7 Hardware Acceleration Capability312.7.1 Checksum Offloading312.7.2 TCP Segmentation312.8 Buffer and Descriptor Structure31Receive and Transmit Description 3333.1 Introduction333.2 Packet Reception333.2.1 Packet Address Filtering333.2.2 Receive Data Storage343.2.3 Receive Descriptor Format343.2.3.1 Receive Descriptor Status Field353.2.3.2 Receive Descriptor Errors Field363.2.3.3 Receive Descriptor Special Field383.2.4 Receive Descriptor Fetching393.2.5 Receive Descriptor Write-Back403.2.5.1 Receive Descriptor Packing403.2.5.2 Null Descriptor Padding403.2.6 Receive Descriptor Queue Structure403.2.7 Receive Interrupts423.2.7.1 Receive Timer Interrupt423.2.7.2 Small Receive Packet Detect443.2.7.3 Receive Descriptor Minimum Threshold (ICR.RXDMT)453.2.7.4 Receiver FIFO Overrun453.2.8 82544GC/EI Receive Interrupts453.2.9 Receive Packet Checksum Offloading453.2.9.1 MAC Address Filter473.2.9.2 SNAP/VLAN Filter483.2.9.3 IPv4 Filter483.2.9.4 IPv6 Filter483.2.9.5 UDP/TCP Filter483.3 Packet Transmission483.3.1 Transmit Data Storage493.3.2 Transmit Descriptors493.3.3 Legacy Transmit Descriptor Format503.3.3.1 Transmit Descriptor Command Field Format523.3.3.2 Transmit Descriptor Status Field Format533.3.4 Transmit Descriptor Special Field Format543.3.5 TCP/IP Context Transmit Descriptor Format553.3.6 TCP/IP Context Descriptor Layout563.3.6.1 TCP/UDP Offload Transmit Descriptor Command Field583.3.6.2 TCP/UDP Offload Transmit Descriptor Status Field603.3.7 TCP/IP Data Descriptor Format603.3.7.1 TCP/IP Data Descriptor Command Field623.3.7.2 TCP/IP Data Descriptor Status Field633.3.7.3 TCP/IP Data Descriptor Option Field643.3.7.4 TCP/IP Data Descriptor Special Field643.4 Transmit Descriptor Ring Structure653.4.1 Transmit Descriptor Fetching673.4.2 Transmit Descriptor Write-back673.4.3 Transmit Interrupts683.4.3.1 Delayed Transmit Interrupts693.5 TCP Segmentation693.5.1 Assumptions703.5.2 Transmission Process703.5.2.1 TCP Segmentation Data Fetch Control713.5.3 TCP Segmentation Performance713.5.4 Packet Format713.5.5 TCP Segmentation Indication723.5.6 TCP Segmentation Use of Multiple Data Descriptors733.5.7 IP and TCP/UDP Headers743.5.8 Transmit Checksum Offloading with TCP Segmentation783.5.9 IP/TCP/UDP Header Updating793.5.9.1 TCP/IP/UDP Header for the First Frame813.5.9.2 TCP/IP/UDP Header for the Subsequent Frames813.5.9.3 TCP/IP/UDP Header for the Last Frame823.6 IP/TCP/UDP Transmit Checksum Offloading82PCI Local Bus Interface 4854.1 PCI Configuration854.1.1 PCI-X Configuration Registers934.1.1.1 PCI-X Capability ID934.1.1.2 Next Capability934.1.1.3 PCI-X Command944.1.1.4 PCI-X Status954.1.2 Reserved and Undefined Addresses964.1.3 Message Signaled Interrupts974.1.3.1 Message Signaled Interrupt Configuration Registers974.2 Commands994.3 PCI/PCI-X Command Usage1014.3.1 Memory Write Operations1014.3.1.1 MWI Bursts1024.3.1.2 MW Bursts1034.3.2 Memory Read Operations1034.3.2.1 PCI-X Command Usage1034.4 Cache Line Information1044.4.1 Target Transaction Termination1054.5 Interrupt Assignment (82547GI/EI Only)1054.6 LAN Disable1054.7 CardBus Application (82541PI/GI/EI Only)106EEPROM Interface 51075.1 General Overview1075.2 Component Identification Via Programming Interface1085.3 EEPROM Device and Interface1095.3.1 Software Access1105.4 Signature and CRC Fields1105.5 EEUPDATE Utility1115.5.1 Command Line Parameters1115.6 EEPROM Address Map1125.6.1 Ethernet Address (Words 00h-02h)1175.6.2 Software Compatibility Word (Word 03h)1175.6.3 SerDes Configuration (Word 04h)1185.6.4 EEPROM Image Version (Word 05h)1185.6.5 Compatibility Fields (Word 05h - 07h)1185.6.6 PBA Number (Word 08h, 09h)1185.6.7 Initialization Control Word 1 (Word 0Ah)1195.6.8 Subsystem ID (Word 0Bh)1205.6.9 Subsystem Vendor ID (Word 0Ch)1205.6.10 Device ID (Word 0Dh, 11h)1215.6.11 Vendor ID (Word 0Eh)1215.6.12 Initialization Control Word 2 (Word 0Fh)1215.6.13 PHY Register Address Data (Words 10h, 11h, and 13h - 1Eh)1235.6.14 OEM Reserved Words (Words 10h, 11h, 13h - 1Fh)1235.6.15 EEPROM Size (Word 12h)1235.6.16 Common Power (Word 12h)1235.6.17 Software Defined Pins Control (Word 10h, 20h)1235.6.18 CSA Port Configuration 2 (Word 21h)1255.6.19 Circuit Control (Word 21h)1265.6.20 D0 Power (Word 22h high byte)1265.6.21 D3 Power (Word 22h low byte)1265.6.22 Reserved Words (23h - 2Eh)1265.6.23 Reserved Words (23h - 2Fh)1265.6.24 Management Control (Word 13h, 23h)1275.6.25 SMBus Slave Address (Word 14h low byte, 24h low byte)1285.6.26 Initialization Control 3 (Word 14h high byte, 24h high byte)1295.6.27 IPv4 Address (Words 15h - 16h and 25h - 26h)1305.6.28 IPv6 Address (words 17h - 1Eh1 and 27h - 2Eh)1305.6.29 LED Configuration Defaults (Word 2Fh)1315.6.30 Boot Agent Main Setup Options (Word 30h)1315.6.31 Boot Agent Configuration Customization Options (Word 31h)1335.6.32 Boot Agent Configuration Customization Options (Word 32h)1355.6.33 IBA Capabilities (Word 33h)1365.6.34 IBA Secondary Port Configuration (Words 34h-35h)1365.6.35 Checksum Word Calculation (Word 3Fh)1375.6.36 82546GB/EB Dual-Channel Fiber Wake on LAN (WOL) Mode and Functionality (Word 0Ah, 20h)1375.6.37 EEPROM Images1375.7 Parallel FLASH Memory138FLASH Memory Interface 71417.1 FLASH Interface Operation1417.2 FLASH Control and Accesses1417.2.1 Read Accesses1427.2.2 Write Accesses142Power Management 61456.1 Introduction to Power Management1456.2 Assumptions1456.3 D3cold support1466.3.1 Power States1466.3.1.1 Dr State1476.3.1.2 D0u State1476.3.1.3 D0a (D0 active)1486.3.1.4 D31486.3.2 Timing1486.3.2.1 Power Up (Off to Dr to D0u to D0a)1496.3.2.2 Transition From D0a to D3 and Back Without PCI Reset1506.3.2.3 Transition From D0a to D3 and Back with PCI Reset1516.3.2.4 PCI Reset Without Transition to D31526.3.3 PCI Power Management Registers1536.3.3.1 Capability ID 1 Byte Offset = 0 (RO)1536.3.3.2 Next Item Pointer 1 Byte Offset = 1 (RO)1536.3.3.3 Power Management Capabilities - (PMC) 2 Bytes Offset = 2 (RO)1546.3.3.4 Power Management Control / Status Register - (PMCSR) 2 Bytes Offset = 4 (RO)1556.3.3.5 PMCSR_BSE Bridge Support Extensions 1 Byte Offset = 6 (RO)1566.3.3.6 Data Register 1 Byte Offset = 7 (RO)1566.4 Wakeup1576.4.1 Advanced Power Management Wakeup1576.4.2 ACPI Power Management Wakeup1586.4.3 Wakeup Packets1596.4.3.1 Pre-Defined Filters1596.4.3.2 Directed IPv6 Packet1646.4.3.3 Flexible Filter1656.4.3.4 IPv6 Neighbor Discovery Filter1666.4.3.5 Wakeup Packet Storage167Ethernet Interface 81698.1 Introduction1698.2 Link Interfaces Overview1698.2.1 Internal SerDes Interface/TBI Mode– 1Gb/s1708.2.1.1 Gigabit Physical Coding Sub-Layer (PCS) for the Internal SerDes1708.2.1.2 8B10B Encoding/Decoding1708.2.1.3 Code Groups and Ordered Sets1718.2.2 GMII – 1 Gb/s1718.2.3 MII – 10/100 Mb/s1728.3 Internal Interface1728.4 Duplex Operation1728.4.1 Full Duplex1738.4.2 Half Duplex1738.4.2.1 Carrier Extension (1000 Mb/s Only)1748.4.2.2 Packet Bursting1748.5 Auto-Negotiation and Link Setup1758.6 Auto-Negotiation and Link Setup1758.6.1 Link Configuration in Internal Serdes/TBI Mode1768.6.1.1 Link Speed1768.6.1.2 Auto-Negotiation1768.6.1.3 Hardware Auto-Negotiation1778.6.1.4 Software Auto-Negotiation1788.6.1.5 Forcing Link1798.6.2 Internal GMII/MII Mode1798.6.2.1 Auto-Negotiation1798.6.2.2 Link Speed1808.6.2.3 Duplex1818.6.2.4 MII Management Registers1818.6.2.5 Comments Regarding Forcing Link1818.6.3 Internal SerDes Mode Control Bit Resolution1828.6.4 Internal PHY Mode Control Bit Resolution1838.6.5 Loss of Signal/Link Status Indication1858.6.5.1 Internal Serdes Mode1858.6.5.2 Internal PHY Mode1858.7 10/100 Mb/s Specific Performance Enhancements1868.7.1 Adaptive IFS1868.7.2 Flow Control1878.7.3 MAC Control Frames & Reception of Flow Control Packets1878.7.4 Discard PAUSE Frames and Pass MAC Control Frames1898.7.5 Transmission of PAUSE Frames1908.7.6 Software Initiated PAUSE Frame Transmission1908.7.7 External Control of Flow Control Operation190802.1q VLAN Support 91939.1 802.1q VLAN Packet Format1939.1.1 802.1q Tagged Frames1939.2 Transmitting and Receiving 802.1q Packets1949.2.1 Adding 802.1q Tags on Transmits1949.2.2 Stripping 802.1q Tags on Receives1949.3 802.1q VLAN Packet Filtering194Configurable LED Outputs 1019710.1 Configurable LED Outputs19710.1.1 Selecting an LED Output Source19710.1.2 Polarity Inversion19810.1.3 Blink Control198PHY Functionality and Features 1120111.1 Auto-Negotiation20111.1.1 Overview20111.1.2 Next Page Exchanges20211.1.3 Register Update20211.1.4 Status20311.2 MDI/MDI-X Crossover (copper only)20311.2.1 Polarity Correction (copper only)20411.2.2 10/100 Downshift (82540EP/EM Only)20411.3 Cable Length Detection (copper only)20511.4 PHY Power Management (copper only)20511.4.1 Link Down – Energy Detect (copper only)20511.4.2 D3 State, No Link Required (copper only)20611.4.3 D3 Link-Up, Speed-Management Enabled (copper only)20611.4.4 D3 Link-Up, Speed-Management Disabled (copper only)20611.5 Initialization20711.5.1 MDIO Control Mode20711.6 Determining Link State20811.6.1 False Link20911.6.2 Forced Operation20911.6.3 Auto Negotiation21011.6.4 Parallel Detection21011.7 Link Criteria21011.7.1 1000BASE-T21011.7.2 100BASE-TX21011.7.3 10BASE-T21111.8 Link Enhancements21111.8.1 SmartSpeed21111.8.1.1 Using SmartSpeed21111.8.2 Flow Control21111.9 Management Data Interface21211.10 Low Power Operation21211.10.1 Powerdown via the PHY Register21311.10.2 Smart Power-Down21311.11 1000 Mbps Operation21311.11.1 Introduction21311.11.2 Transmit Functions21511.11.2.1 Scrambler21511.11.3 Transmit FIFO21511.11.3.1 Transmit Phase-Locked Loop PLL21511.11.3.2 Trellis Encoder21511.11.3.3 4DPAM5 Encoder21511.11.3.4 Spectral Shaper21611.11.3.5 Low-Pass Filter21611.11.3.6 Line Driver21611.11.3.7 Transmit/Receive Flow21611.11.4 Receive Functions21711.11.4.1 Hybrid21711.11.4.2 Automatic Gain Control21711.11.4.3 Timing Recovery21711.11.4.4 Analog-to-Digital Converter21711.11.4.5 Digital Signal Processor21711.11.4.6 Descrambler21811.11.4.7 Viterbi Decoder/Decision Feedback Equalizer (DFE)21811.11.4.8 4DPAM5 Decoder21811.12 100 Mbps Operation21811.13 10 Mbps Operation21811.13.1 Link Test21911.13.2 10Base-T Link Failure Criteria and Override21911.13.3 Jabber21911.13.4 Polarity Correction21911.13.5 Dribble Bits21911.14 PHY Line Length Indication219Dual Port Characteristics 1222112.1 Introduction22112.2 Features of Each MAC22112.2.1 PCI/PCI-X interface22112.2.2 MAC Configuration Register Space22312.2.3 SDP, LED, INT# output22312.3 Shared EEPROM22412.3.1 EEPROM Map22412.3.2 EEPROM Arbitration22412.4 Shared FLASH22512.4.1 FLASH Access Contention22512.5 LAN Disable22612.5.1 Overview22612.5.2 Values Sampled on Reset22612.5.3 Multi-Function Advertisement22712.5.4 Interrupt Use22712.5.5 Power Reporting22712.5.6 Summary228Register Descriptions 1322913.1 Introduction22913.2 Register Conventions22913.2.1 Memory and I/O Address Decoding23013.2.1.1 Memory-Mapped Access to Internal Registers and Memories23013.2.1.2 Memory-Mapped Access to FLASH23013.2.1.3 Memory-Mapped Access to Expansion ROM23013.2.2 I/O-Mapped Internal Register, Internal Memory, and Flash23113.2.2.1 IOADDR23113.2.2.2 IODATA23113.3 PCI-X Register Access Split23713.4 Main Register Descriptions23813.4.1 Device Control Register23813.4.2 Device Status Register24313.4.3 EEPROM/Flash Control & Data Register24613.4.4 EEPROM Read Register24813.4.5 Flash Access25013.4.6 Extended Device Control Register25113.4.7 MDI Control Register25613.4.7.1 PHY Registers25813.4.8 Flow Control Address Low29713.4.9 Flow Control Address High29713.4.10 Flow Control Type29813.4.11 VLAN Ether Type29813.4.12 Flow Control Transmit Timer Value29913.4.13 Transmit Configuration Word Register30013.4.14 Receive Configuration Word Register30113.4.15 LED Control30313.4.15.1 MODE Encodings for LED Outputs130413.4.16 Packet Buffer Allocation30613.4.17 Interrupt Cause Read Register30713.4.18 Interrupt Throttling Register30913.4.19 Interrupt Cause Set Register31013.4.20 Interrupt Mask Set/Read Register31113.4.21 Interrupt Mask Clear Register31213.4.22 Receive Control Register31413.4.23 Flow Control Receive Threshold Low31813.4.24 Flow Control Receive Threshold High31913.4.25 Receive Descriptor Base Address Low32013.4.26 Receive Descriptor Base Address High32013.4.27 Receive Descriptor Length32113.4.28 Receive Descriptor Head32113.4.29 Receive Descriptor Tail32213.4.30 Receive Delay Timer Register32213.4.31 Receive Interrupt Absolute Delay Timer32313.4.32 Receive Small Packet Detect Interrupt32413.4.33 Transmit Control Register32413.4.34 Transmit IPG Register32613.4.35 Adaptive IFS Throttle - AIT32813.4.36 Transmit Descriptor Base Address Low32913.4.37 Transmit Descriptor Base Address High33013.4.38 Transmit Descriptor Length33013.4.39 Transmit Descriptor Head33113.4.40 Transmit Descriptor Tail33213.4.41 Transmit Interrupt Delay Value33213.4.42 TX DMA Control (82544GC/EI only)33313.4.43 Transmit Descriptor Control33313.4.44 Transmit Absolute Interrupt Delay Value33513.4.45 TCP Segmentation Pad And Minimum Threshold33613.4.46 Receive Descriptor Control33813.4.47 Receive Checksum Control33913.5 Filter Registers34113.5.1 Multicast Table Array34113.5.2 Receive Address Low34313.5.3 Receive Address High34313.5.4 VLAN Filter Table Array34413.6 Wakeup Registers34513.6.1 Wakeup Control Register34513.6.2 Wakeup Filter Control Register34613.6.3 Wakeup Status Register34713.6.4 IP Address Valid34913.6.5 IPv4 Address Table35013.6.6 IPv6 Address Table35113.6.7 Wakeup Packet Length35213.6.8 Wakeup Packet Memory (128 Bytes)35213.6.9 Flexible Filter Length Table35213.6.10 Flexible Filter Mask Table35313.6.11 Flexible Filter Value Table35413.7 Statistics Registers35413.7.1 CRC Error Count35513.7.2 Alignment Error Count35513.7.3 Symbol Error Count35613.7.4 RX Error Count35613.7.5 Missed Packets Count35713.7.6 Single Collision Count35713.7.7 Excessive Collisions Count35813.7.8 Multiple Collision Count35813.7.9 Late Collisions Count35913.7.10 Collision Count35913.7.11 Defer Count36013.7.12 Transmit with No CRS36013.7.13 Sequence Error Count36113.7.14 Carrier Extension Error Count36113.7.15 Receive Length Error Count36213.7.16 XON Received Count36213.7.17 XON Transmitted Count36313.7.18 XOFF Received Count36313.7.19 XOFF Transmitted Count36313.7.20 FC Received Unsupported Count36413.7.21 Packets Received (64 Bytes) Count36413.7.22 Packets Received (65-127 Bytes) Count36513.7.23 Packets Received (128-255 Bytes) Count36513.7.24 Packets Received (256-511 Bytes) Count36613.7.25 Packets Received (512-1023 Bytes) Count36613.7.26 Packets Received (1024 to Max Bytes) Count36713.7.27 Good Packets Received Count36713.7.28 Broadcast Packets Received Count36813.7.29 Multicast Packets Received Count36813.7.30 Good Packets Transmitted Count36913.7.31 Good Octets Received Count36913.7.32 Good Octets Transmitted Count37013.7.33 Receive No Buffers Count37013.7.34 Receive Undersize Count37113.7.35 Receive Fragment Count37113.7.36 Receive Oversize Count37213.7.37 Receive Jabber Count37213.7.38 Management Packets Received Count37313.7.39 Management Packets Dropped Count137413.7.40 Management Pkts Transmitted Count37413.7.41 Total Octets Received37413.7.42 Total Octets Transmitted37513.7.43 Total Packets Received37613.7.44 Total Packets Transmitted37613.7.45 Packets Transmitted (64 Bytes) Count37713.7.46 Packets Transmitted (65-127 Bytes) Count37713.7.47 Packets Transmitted (128-255 Bytes) Count37813.7.48 Packets Transmitted (256-511 Bytes) Count37813.7.49 Packets Transmitted (512-1023 Bytes) Count37913.7.50 Packets Transmitted (1024 Bytes or Greater) Count37913.7.51 Multicast Packets Transmitted Count38013.7.52 Broadcast Packets Transmitted Count38013.7.53 TCP Segmentation Context Transmitted Count38113.7.54 TCP Segmentation Context Transmit Fail Count38113.8 Diagnostics Registers38213.8.1 Receive Data FIFO Head Register38213.8.2 Receive Data FIFO Tail Register38213.8.3 Receive Data FIFO Head Saved Register38313.8.4 Receive Data FIFO Tail Saved Register38313.8.5 Receive Data FIFO Packet Count38413.8.6 Transmit Data FIFO Head Register38413.8.7 Transmit Data FIFO Tail Register38513.8.8 Transmit Data FIFO Head Saved Register38513.8.9 Transmit Data FIFO Tail Saved Register38613.8.10 Transmit Data FIFO Packet Count38613.8.11 Packet Buffer Memory387General Initialization and Reset Operation 1438914.1 Introduction38914.2 Power Up State38914.3 General Configuration38914.4 Receive Initialization39014.5 Transmit Initialization39114.5.1 Signal Interface39414.5.2 GMII/MII Features not Supported39514.5.3 Avoiding GMII Test Mode(s)39614.5.4 MAC Configuration39614.5.5 Link Setup39714.6 PHY Initialization (10/100/1000 Mb/s Copper Media)39814.7 Reset Operation39914.8 Initialization of Statistics402Diagnostics and Testability 1540315.1 Diagnostics40315.1.1 FIFO State40315.1.2 FIFO Data40315.1.3 Loopback40315.1.3.1 Internal Loopback40415.2 Testability40415.2.1 EXTEST Instruction40515.2.2 SAMPLE/PRELOAD Instruction40515.2.3 IDCODE Instruction40515.2.4 BYPASS Instruction405Appendix (Changes From 82544EI/82544GC) A407A.1 Introduction407A.2 New Features407A.3 Register Changes408Appendix (82540EP/EM and 82545GM/EM Differences) B409B.1 Introduction409B.2 82540EP/EM Differences409サイズ: 2.15MBページ数: 410Language: Englishマニュアルを開く