ユーザーズマニュアル目次Contents3Revision History8Intel 8255x 10/100 Mbps Ethernet Controller Family1Introduction 191.1 Scope91.2 Document Conventions101.2.1 Device References101.2.2 Numbering101.2.3 Signal Name Representation101.2.4 Memory Alignment Terminology10Adapter and Controller Overview 2132.1 Adapter Block Diagram13Figure 1. 82557 Network Interface Card Block Diagram132.2 Intel Fast Ethernet MAC Features142.2.1 82557 Features142.2.2 82558 Features142.2.3 82559, 82550, 82551, and 82562 Features152.2.3.1 82559ER Features152.2.3.2 82551ER Features152.3 Working with the Physical Layer15Power Management Interface 3173.1 Low Power Mode Requirements173.2 Device Power States173.3 Power Management Registers173.4 Link Operation18PCI Interface 4194.1 PCI Configuration Space19Table 1. PCI Configuration Space194.1.1 Vendor ID (Offset 0)204.1.2 Device ID (Offset 2)204.1.3 Command Register (Offset 4)20Figure 2. Command Register204.1.4 Status Register (Offset 6)20Figure 3. Command Register214.1.5 Revision (Offset 8)21Table 2. Device and Revision ID214.1.6 Class Code (Offset 9)224.1.7 Cache Line Size (Offset C)22Figure 4. Cache Line Size224.1.8 Latency Timer (Offset D)224.1.9 Header Type (Offset E)224.1.10 Built in Self Test (Offset F)23Figure 5. Base Address Register for Memory Mapping23Figure 6. Base Address Register for I/O Mapping23Table 3. Base Address Register Summary244.1.11 Subsystem ID (Offset 2C)244.1.12 Subsystem Vendor ID (Offset 2E)244.1.13 Expansion ROM Base Address Register (Offset 30)24Figure 7. Expansion ROM Base Address Register254.1.14 The Capabilities Pointer (Offset 34)254.1.15 Interrupt Line (Offset 3C)254.1.16 Interrupt Pin (Offset 3D)254.1.17 Max_Lat / Min_Gnt (Offset 3E)264.1.18 Power Management PCI Configuration Registers264.1.18.1 Capability Identifier (Offset DC)264.1.18.2 Next Item Pointer (Offset DD)264.1.18.3 Power Management Capabilities (Offset DE)26Table 4. Power Management Capabilities264.1.18.4 Power Management Control/Status (Offset E0)27Table 5. Power Management Control/Status Register284.1.18.5 Ethernet Power Consumption Registers (Offset E2h)29Table 6. Power Consumption / Dissipation Reporting294.2 PCI Command Usage29Table 7. Generated PCI Commands304.2.1 Memory Write and Invalidate304.2.2 Read Align314.2.3 Odd Byte Alignment Support31EEPROM Interface 533Host Software Interface 6356.1 The Shared Memory Architecture35Figure 8. 8255x Memory Architecture366.2 Initializing the LAN Controller37Table 8. Reset Commands376.2.1 LAN Controller Addressing Format37Table 9. Device Addressing Formats38Table 10. Alignment Requirements for 8255x Data Structures396.3 Controlling the Device396.3.1 Control / Status Registers (CSR)39Table 11. Control / Status Register406.3.2 System Control Block (SCB)41Table 12. System Control Block426.3.2.1 SCB Status Word42Figure 9. SCB Status Word42Table 13. SCB Status Word Bits Descriptions436.3.2.2 SCB Command Word44Figure 10. SCB Command Word44Table 14. SCB Command Word Bits Descriptions456.3.2.3 SCB General Pointer47Table 15. SCB General Pointer for the CU Command47Table 16. SCB General Pointer for the RU Command486.3.2.4 Statistical Counters48Table 17. Statistical Counters486.3.3 PORT Interface51Table 18. Port Register Location51Table 19. Port Selection Function516.3.3.1 PORT Software Reset526.3.3.2 PORT Self-test52Figure 11. Self-Test Results Format526.3.3.3 Port Selective Reset536.3.3.4 Port Dump536.3.3.5 PORT Dump Wake-up53Table 20. Dump Wake-up Data Structure536.3.4 EEPROM Control Register53Table 21. EEPROM Control Register Locations546.3.4.1 CPU Accesses to the EEPROM54Figure 12. EEPROM Control Register54Table 22. EEPROM Control Register Bits Definitions54Table 23. EEPROM Opcode Summary (64-register EEPROM)556.3.4.2 Software Determination of EEPROM Size556.3.4.3 Software Read Access from the EEPROM56Figure 13. EEPROM Read Timing Diagram566.3.4.4 Software Write Access to the EEPROM576.3.5 Management Data Interface Control Register57Table 24. MDI Control Register Location57Table 25. Management Data Pins586.3.5.1 MDI Control Register58Table 26. MDI Control Register Bits586.3.5.2 MDI Write cycle586.3.5.3 MDI Read cycle596.3.6 Receive Byte Count Register59Table 27. Receive Byte Count Register Location606.3.7 Early Receive Interrupt60Table 28. Early Receive Interrupt Register Location606.3.8 Flow Control Register61Table 29. Flow Control Registers Location61Table 30. Flow Control Threshold Values626.3.9 Power Management Driver Register62Table 31. Power Management Driver Register Location63Table 32. Power Management Driver Register636.3.10 General Control Register64Table 33. General Control Register Location64Table 34. General Control Register646.3.11 General Status Register64Table 35. General Status Register Location64Table 36. General Status Register656.4 Shared Memory Structures656.4.1 Action Commands and Operating Modes65Table 37. Operation Codes656.4.1.1 General Action Command Format66Figure 14. General Action Command Format666.4.1.1.1 Beginning Execution666.4.1.1.2 Completing Execution666.4.2 Specific Action Commands676.4.2.1 NOP (000b)67Figure 15. NOP Command Format676.4.2.2 Individual Address Setup (001b)68Figure 16. Individual Address Setup Command Format686.4.2.3 Configure (010b)69Figure 17. Configure Command Format70Table 38. 82557 Configuration Byte Map70Table 39. 82558 Configuration Byte Map72Table 40. 82559 Configuration Byte Map736.4.2.3.1 Configuration Parameters73Table 41. 82557 Dual-Port FIFO Settings - Transmit74Table 42. 82557 Dual-Port FIFO Settings - Receive75Table 43. 82558 and 82559 Dual-Port FIFO Settings - Transmit75Table 44. 82558 and 82559 Dual-Port FIFO Settings - Receive76Table 45. Extended Statistics Functionality80Table 46. Pre-amble Length83Table 47. 82558 B-step Configuration Block ARP Frame IP Address84Table 48. 82558 B-step ARP Frame IP Address Mapping85Table 49. Full Duplex Functionality876.4.2.4 Multicast Setup (011b)90Figure 18. Multicast Setup Command Format906.4.2.5 Transmit (100b)91Figure 19. Transmit Command Format91Figure 20. Transmit Buffer Descriptor936.4.2.5.1 Dynamic TBD Mode946.4.2.5.2 Transmit Command Operation956.4.2.5.3 Framing Operation966.4.2.5.4 Delayed CNA Interrupts976.4.2.6 Load Microcode (101b)98Figure 21. Load Microcode Command Format986.4.2.7 Dump (110b)99Figure 22. Dump Command Format99Table 50. Dump Data Bytes (0-79)100Table 51. Dump Data Dwords (20-148)1036.4.2.8 Diagnose (111b)105Figure 23. Diagnose Command Format1056.4.3 Receive Operation1076.4.3.1 Receive Frame Area1076.4.3.1.1 Simplified RFA Structure107Figure 24. Simplified Memory Structure1086.4.3.1.2 Receive Frame Descriptor Format108Figure 25. Receive Frame Descriptor Format108Table 52. RFD Status Bit Descriptions109Table 53. Actual Count in Header RFD1106.4.3.2 Initial Receive Frame Area Structure1106.4.3.3 Operation of Frame Reception1106.4.3.3.1 Configuring the Next RFD1116.4.3.3.2 Close Frame1116.4.3.3.3 Completion of Reception1116.4.3.4 No Buffer Performance Improvements (82558 and 82559)1126.4.3.4.1 TCP/UDP Checksum Support (82559 only)112Example 1. 82559 Checksum Calculation112Example 2. Numerical Calculation1136.5 Command Unit and Receive Unit Operation1136.5.1 Starting and Completing Control Commands1136.5.2 Generating and Acknowledging Interrupts1136.5.3 Command Unit Control1146.5.3.1 CU Start Command1146.5.3.2 CU Resume Command1156.5.3.3 CU Control Commands Response115Table 54. CU Control Commands: Actions at Acceptance Time115Table 55. CU Activities Performed at the End of Execution1156.5.4 Receive Unit Control116Table 56. RU Control Commands: Actions at Acceptance Time1166.5.4.1 RU Start Command1176.5.4.2 RU Resume Command1186.5.4.3 RU Abort Command1186.5.5 Updating SCB Status1186.6 Flow Control1186.6.1 PHY Based Flow Control1196.6.2 Frame Based Flow Control1196.6.2.1 Protocol Description119Table 57. Flow Control Frame Format1206.6.2.2 Pause Operation1206.6.2.3 Flow Control Functionality1206.6.2.3.1 Transmit Flow Control1216.6.2.3.2 Receive Flow Control121Example 3. Configured “FC Delay” (011Fh)122Example 4. Configured “FC Delay” (0017h)122Table 58. Flow Control Configuration Bits1236.6.3 Priority Aware Frame Based Flow Control1236.6.3.1 Priority Flow Control Operation1236.6.3.2 Flow Control Frame Format1236.6.4 Half Duplex Flow Control1246.7 Collision Backoff Modification in Switched Environments124Physical Layer Interface 71257.1 Management Data Interface (MDI)125Figure 26. Management Frame Structure1267.2 MDI Register Set126Table 59. MDI Register Set126Table 60. 82555 MDI Register Set1267.2.1 Control Register: Register 01277.2.2 Status Register: Register 11287.2.3 Identification Registers: Registers 2 and 3129Table 61. 24-bit OUI Identification Number129Table 62. MDI Identification Registers 2 and 3: PHY ID Encoding1297.2.4 Auto-Negotiation Advertisement Register: Register 41307.2.5 Auto-Negotiation Link Partner Ability Register: Register 51307.2.6 Auto-Negotiation Expansion Register: Register 61317.3 Intel 82555 Specific Registers1327.3.1 Status and Control Register: Register 161327.3.2 Special Control Register: Register 171337.3.3 Clock Synthesis Test and Control Register: Register 181347.3.4 100BASE-TX Receive False Carrier Counter: Register 191347.3.5 100Base-TX Receive Disconnect Counter: Register 201347.3.6 100BASE-TX Receive Error Frame Counter: Register 211357.3.7 Receive Symbol Error Counter: Register 221357.3.8 100BASE-TX Receive EOF Error Counter: Register 231357.3.9 10BASE-T Receive EOF Error Counter: Register 241357.3.10 10BASE-T Transmit Jabber Detect Counter: Register 251357.3.11 Equalizer Control and Status Register: Register 261367.3.12 Special Control Register: Register 27137Table 63. LED Switch Control1387.4 Auto-Negotiation Functionality1387.4.1 Description138Table 64. Technology Ability Field Bit Assignments139Table 65. Technology Priority1397.4.2 Parallel Detection1397.5 Vendor-Specific PHY Programming1407.5.1 Intel 82555 TX PHY1407.5.2 82558 and 82559 Embedded PHY Unit1407.5.2.1 PHY Stand Alone (PHYSA) Mode141Programming Recommendations 81438.1 Adapter Initialization1438.1.1 8255x Initialization1438.1.2 PHY Detection and Initialization1438.1.3 NOS Specific Initialization1448.2 Transmit Processing1448.3 Frame Reception1448.4 Interrupt Processing145Wake-up Functionality A147A.1 Wake-up Capability147A.2 Low Power Modes148A.3 Power Management Context After Reset148A.3.1 Auxiliary Power Support149A.3.2 Auxiliary Power Non-support149A.4 Fixed Packet Filtering149A.4.1 Magic Packet*150A.4.2 Address Matching150A.4.3 ARP Packet Filtering150A.4.4 Configuration Bits for Fixed Wake-up filters151Table 66. Fixed Wake-up Configuration Bits151A.5 Link Status Event152A.6 Flexible Packet Filtering152A.6.1 Flexible Filtering Terminology153A.6.2 Flexible Filtering Limitations153A.6.3 Wake-up Packet Storage154A.7 82559 and Later Generation Device Implementation154A.7.1 Load Programmable Filter Command Structures154Figure 27. Command Block Structure154Example 5. 82559 Wake-up Programming156A.7.2 CRC Word calculation of a Flexible Filter158A.7.3 Port Dump Wake Up Packet158Table 67. 82559 Port Commands158Table 68. Dump Data Structure159A.7.4 Power Management Software Flow159A.7.4.1 Power Down without Wake-up Capabilities159A.7.4.2 Power Down with Wake-up Capabilities160A.7.4.3 Wake-up Sequence160A.7.4.4 Dummy Wake-up Sequence16182550 and 82551QM Specific Information B163B.1 IPCB163Table 69. IPCB Structure163Table 70. IP Activation Bits (Byte 13)163Table 71. IP Activation Bits (Byte 12)163Table 72. IPCB Fields164B.1.1 Maximum TCP Payload / TBD Number and Transmit Threshold165B.2 82550 Checksum Operation166B.2.1 Driver Interface166Table 73. IPCB Structure Checksum Offload166B.2.2 IPCB Field Assignment167B.2.2.1 Parameters167B.2.2.2 Status168B.2.2.3 Configuration168B.2.3 Data Flow168B.2.4 Tunneling Support169B.3 Large Send169B.3.1 Rationale169B.3.2 Driver interface169Table 74. IPCB Structure Large Send170B.3.3 IPCB Large Send170B.3.3.1 Parameters170B.3.4 Data Flow171B.3.4.1 Headers Parsing171B.3.4.2 First Frame Processing171B.3.4.3 Intermediate Frames Processing172B.3.4.4 Handling the Last Frame173B.3.4.5 Performance Considerations174B.3.5 Features Co-existence174B.3.5.1 Large Send and Checksum174B.3.5.2 Large Send and Software Parsing174B.3.5.3 Large Send and Scheduling Assist174B.4 RCV Checksum Processing174B.4.1 Data Flow174B.4.1.1 Frame Types175B.4.1.2 Verification Types175B.4.2 82559 Compatibility175B.5 VLAN Tagging175サイズ: 992KBページ数: 175Language: Englishマニュアルを開く