Intel 82559 マニュアル

目次

• Contents

  3
• Revision History

  8
• Intel 8255x 10/100 Mbps Ethernet Controller Family

  1
  • Introduction 1

    9
    • 1.1 Scope

      9
    • 1.2 Document Conventions

      10
      • 1.2.1 Device References

        10
      • 1.2.2 Numbering

        10
      • 1.2.3 Signal Name Representation

        10
      • 1.2.4 Memory Alignment Terminology

        10
  • Adapter and Controller Overview 2

    13
    • 2.1 Adapter Block Diagram

      13
      • Figure 1. 82557 Network Interface Card Block Diagram

        13
    • 2.2 Intel Fast Ethernet MAC Features

      14
      • 2.2.1 82557 Features

        14
      • 2.2.2 82558 Features

        14
      • 2.2.3 82559, 82550, 82551, and 82562 Features

        15
        • 2.2.3.1 82559ER Features

          15
        • 2.2.3.2 82551ER Features

          15
    • 2.3 Working with the Physical Layer

      15
  • Power Management Interface 3

    17
    • 3.1 Low Power Mode Requirements

      17
    • 3.2 Device Power States

      17
    • 3.3 Power Management Registers

      17
    • 3.4 Link Operation

      18
  • PCI Interface 4

    19
    • 4.1 PCI Configuration Space

      19
      • Table 1. PCI Configuration Space

        19
      • 4.1.1 Vendor ID (Offset 0)

        20
      • 4.1.2 Device ID (Offset 2)

        20
      • 4.1.3 Command Register (Offset 4)

        20
        • Figure 2. Command Register

          20
      • 4.1.4 Status Register (Offset 6)

        20
        • Figure 3. Command Register

          21
      • 4.1.5 Revision (Offset 8)

        21
        • Table 2. Device and Revision ID

          21
      • 4.1.6 Class Code (Offset 9)

        22
      • 4.1.7 Cache Line Size (Offset C)

        22
        • Figure 4. Cache Line Size

          22
      • 4.1.8 Latency Timer (Offset D)

        22
      • 4.1.9 Header Type (Offset E)

        22
      • 4.1.10 Built in Self Test (Offset F)

        23
        • Figure 5. Base Address Register for Memory Mapping

          23
        • Figure 6. Base Address Register for I/O Mapping

          23
        • Table 3. Base Address Register Summary

          24
      • 4.1.11 Subsystem ID (Offset 2C)

        24
      • 4.1.12 Subsystem Vendor ID (Offset 2E)

        24
      • 4.1.13 Expansion ROM Base Address Register (Offset 30)

        24
        • Figure 7. Expansion ROM Base Address Register

          25
      • 4.1.14 The Capabilities Pointer (Offset 34)

        25
      • 4.1.15 Interrupt Line (Offset 3C)

        25
      • 4.1.16 Interrupt Pin (Offset 3D)

        25
      • 4.1.17 Max_Lat / Min_Gnt (Offset 3E)

        26
      • 4.1.18 Power Management PCI Configuration Registers

        26
        • 4.1.18.1 Capability Identifier (Offset DC)

          26
        • 4.1.18.2 Next Item Pointer (Offset DD)

          26
        • 4.1.18.3 Power Management Capabilities (Offset DE)

          26
          • Table 4. Power Management Capabilities

            26
        • 4.1.18.4 Power Management Control/Status (Offset E0)

          27
          • Table 5. Power Management Control/Status Register

            28
        • 4.1.18.5 Ethernet Power Consumption Registers (Offset E2h)

          29
          • Table 6. Power Consumption / Dissipation Reporting

            29
    • 4.2 PCI Command Usage

      29
      • Table 7. Generated PCI Commands

        30
      • 4.2.1 Memory Write and Invalidate

        30
      • 4.2.2 Read Align

        31
      • 4.2.3 Odd Byte Alignment Support

        31
  • EEPROM Interface 5

    33
  • Host Software Interface 6

    35
    • 6.1 The Shared Memory Architecture

      35
      • Figure 8. 8255x Memory Architecture

        36
    • 6.2 Initializing the LAN Controller

      37
      • Table 8. Reset Commands

        37
      • 6.2.1 LAN Controller Addressing Format

        37
        • Table 9. Device Addressing Formats

          38
        • Table 10. Alignment Requirements for 8255x Data Structures

          39
    • 6.3 Controlling the Device

      39
      • 6.3.1 Control / Status Registers (CSR)

        39
        • Table 11. Control / Status Register

          40
      • 6.3.2 System Control Block (SCB)

        41
        • Table 12. System Control Block

          42
        • 6.3.2.1 SCB Status Word

          42
          • Figure 9. SCB Status Word

            42
          • Table 13. SCB Status Word Bits Descriptions

            43
        • 6.3.2.2 SCB Command Word

          44
          • Figure 10. SCB Command Word

            44
          • Table 14. SCB Command Word Bits Descriptions

            45
        • 6.3.2.3 SCB General Pointer

          47
          • Table 15. SCB General Pointer for the CU Command

            47
          • Table 16. SCB General Pointer for the RU Command

            48
        • 6.3.2.4 Statistical Counters

          48
          • Table 17. Statistical Counters

            48
      • 6.3.3 PORT Interface

        51
        • Table 18. Port Register Location

          51
        • Table 19. Port Selection Function

          51
        • 6.3.3.1 PORT Software Reset

          52
        • 6.3.3.2 PORT Self-test

          52
          • Figure 11. Self-Test Results Format

            52
        • 6.3.3.3 Port Selective Reset

          53
        • 6.3.3.4 Port Dump

          53
        • 6.3.3.5 PORT Dump Wake-up

          53
          • Table 20. Dump Wake-up Data Structure

            53
      • 6.3.4 EEPROM Control Register

        53
        • Table 21. EEPROM Control Register Locations

          54
        • 6.3.4.1 CPU Accesses to the EEPROM

          54
          • Figure 12. EEPROM Control Register

            54
          • Table 22. EEPROM Control Register Bits Definitions

            54
          • Table 23. EEPROM Opcode Summary (64-register EEPROM)

            55
        • 6.3.4.2 Software Determination of EEPROM Size

          55
        • 6.3.4.3 Software Read Access from the EEPROM

          56
          • Figure 13. EEPROM Read Timing Diagram

            56
        • 6.3.4.4 Software Write Access to the EEPROM

          57
      • 6.3.5 Management Data Interface Control Register

        57
        • Table 24. MDI Control Register Location

          57
        • Table 25. Management Data Pins

          58
        • 6.3.5.1 MDI Control Register

          58
          • Table 26. MDI Control Register Bits

            58
        • 6.3.5.2 MDI Write cycle

          58
        • 6.3.5.3 MDI Read cycle

          59
      • 6.3.6 Receive Byte Count Register

        59
        • Table 27. Receive Byte Count Register Location

          60
      • 6.3.7 Early Receive Interrupt

        60
        • Table 28. Early Receive Interrupt Register Location

          60
      • 6.3.8 Flow Control Register

        61
        • Table 29. Flow Control Registers Location

          61
        • Table 30. Flow Control Threshold Values

          62
      • 6.3.9 Power Management Driver Register

        62
        • Table 31. Power Management Driver Register Location

          63
        • Table 32. Power Management Driver Register

          63
      • 6.3.10 General Control Register

        64
        • Table 33. General Control Register Location

          64
        • Table 34. General Control Register

          64
      • 6.3.11 General Status Register

        64
        • Table 35. General Status Register Location

          64
        • Table 36. General Status Register

          65
    • 6.4 Shared Memory Structures

      65
      • 6.4.1 Action Commands and Operating Modes

        65
        • Table 37. Operation Codes

          65
        • 6.4.1.1 General Action Command Format

          66
          • Figure 14. General Action Command Format

            66
          • 6.4.1.1.1 Beginning Execution

            66
          • 6.4.1.1.2 Completing Execution

            66
      • 6.4.2 Specific Action Commands

        67
        • 6.4.2.1 NOP (000b)

          67
          • Figure 15. NOP Command Format

            67
        • 6.4.2.2 Individual Address Setup (001b)

          68
          • Figure 16. Individual Address Setup Command Format

            68
        • 6.4.2.3 Configure (010b)

          69
          • Figure 17. Configure Command Format

            70
          • Table 38. 82557 Configuration Byte Map

            70
          • Table 39. 82558 Configuration Byte Map

            72
          • Table 40. 82559 Configuration Byte Map

            73
          • 6.4.2.3.1 Configuration Parameters

            73
            • Table 41. 82557 Dual-Port FIFO Settings - Transmit

              74
            • Table 42. 82557 Dual-Port FIFO Settings - Receive

              75
            • Table 43. 82558 and 82559 Dual-Port FIFO Settings - Transmit

              75
            • Table 44. 82558 and 82559 Dual-Port FIFO Settings - Receive

              76
            • Table 45. Extended Statistics Functionality

              80
            • Table 46. Pre-amble Length

              83
            • Table 47. 82558 B-step Configuration Block ARP Frame IP Address

              84
            • Table 48. 82558 B-step ARP Frame IP Address Mapping

              85
            • Table 49. Full Duplex Functionality

              87
        • 6.4.2.4 Multicast Setup (011b)

          90
          • Figure 18. Multicast Setup Command Format

            90
        • 6.4.2.5 Transmit (100b)

          91
          • Figure 19. Transmit Command Format

            91
          • Figure 20. Transmit Buffer Descriptor

            93
          • 6.4.2.5.1 Dynamic TBD Mode

            94
          • 6.4.2.5.2 Transmit Command Operation

            95
          • 6.4.2.5.3 Framing Operation

            96
          • 6.4.2.5.4 Delayed CNA Interrupts

            97
        • 6.4.2.6 Load Microcode (101b)

          98
          • Figure 21. Load Microcode Command Format

            98
        • 6.4.2.7 Dump (110b)

          99
          • Figure 22. Dump Command Format

            99
          • Table 50. Dump Data Bytes (0-79)

            100
          • Table 51. Dump Data Dwords (20-148)

            103
        • 6.4.2.8 Diagnose (111b)

          105
          • Figure 23. Diagnose Command Format

            105
      • 6.4.3 Receive Operation

        107
        • 6.4.3.1 Receive Frame Area

          107
          • 6.4.3.1.1 Simplified RFA Structure

            107
            • Figure 24. Simplified Memory Structure

              108
          • 6.4.3.1.2 Receive Frame Descriptor Format

            108
            • Figure 25. Receive Frame Descriptor Format

              108
            • Table 52. RFD Status Bit Descriptions

              109
            • Table 53. Actual Count in Header RFD

              110
        • 6.4.3.2 Initial Receive Frame Area Structure

          110
        • 6.4.3.3 Operation of Frame Reception

          110
          • 6.4.3.3.1 Configuring the Next RFD

            111
          • 6.4.3.3.2 Close Frame

            111
          • 6.4.3.3.3 Completion of Reception

            111
        • 6.4.3.4 No Buffer Performance Improvements (82558 and 82559)

          112
          • 6.4.3.4.1 TCP/UDP Checksum Support (82559 only)

            112
            • Example 1. 82559 Checksum Calculation

              112
            • Example 2. Numerical Calculation

              113
    • 6.5 Command Unit and Receive Unit Operation

      113
      • 6.5.1 Starting and Completing Control Commands

        113
      • 6.5.2 Generating and Acknowledging Interrupts

        113
      • 6.5.3 Command Unit Control

        114
        • 6.5.3.1 CU Start Command

          114
        • 6.5.3.2 CU Resume Command

          115
        • 6.5.3.3 CU Control Commands Response

          115
          • Table 54. CU Control Commands: Actions at Acceptance Time

            115
          • Table 55. CU Activities Performed at the End of Execution

            115
      • 6.5.4 Receive Unit Control

        116
        • Table 56. RU Control Commands: Actions at Acceptance Time

          116
        • 6.5.4.1 RU Start Command

          117
        • 6.5.4.2 RU Resume Command

          118
        • 6.5.4.3 RU Abort Command

          118
      • 6.5.5 Updating SCB Status

        118
    • 6.6 Flow Control

      118
      • 6.6.1 PHY Based Flow Control

        119
      • 6.6.2 Frame Based Flow Control

        119
        • 6.6.2.1 Protocol Description

          119
          • Table 57. Flow Control Frame Format

            120
        • 6.6.2.2 Pause Operation

          120
        • 6.6.2.3 Flow Control Functionality

          120
          • 6.6.2.3.1 Transmit Flow Control

            121
          • 6.6.2.3.2 Receive Flow Control

            121
            • Example 3. Configured “FC Delay” (011Fh)

              122
            • Example 4. Configured “FC Delay” (0017h)

              122
            • Table 58. Flow Control Configuration Bits

              123
      • 6.6.3 Priority Aware Frame Based Flow Control

        123
        • 6.6.3.1 Priority Flow Control Operation

          123
        • 6.6.3.2 Flow Control Frame Format

          123
      • 6.6.4 Half Duplex Flow Control

        124
    • 6.7 Collision Backoff Modification in Switched Environments

      124
  • Physical Layer Interface 7

    125
    • 7.1 Management Data Interface (MDI)

      125
      • Figure 26. Management Frame Structure

        126
    • 7.2 MDI Register Set

      126
      • Table 59. MDI Register Set

        126
      • Table 60. 82555 MDI Register Set

        126
      • 7.2.1 Control Register: Register 0

        127
      • 7.2.2 Status Register: Register 1

        128
      • 7.2.3 Identification Registers: Registers 2 and 3

        129
        • Table 61. 24-bit OUI Identification Number

          129
        • Table 62. MDI Identification Registers 2 and 3: PHY ID Encoding

          129
      • 7.2.4 Auto-Negotiation Advertisement Register: Register 4

        130
      • 7.2.5 Auto-Negotiation Link Partner Ability Register: Register 5

        130
      • 7.2.6 Auto-Negotiation Expansion Register: Register 6

        131
    • 7.3 Intel 82555 Specific Registers

      132
      • 7.3.1 Status and Control Register: Register 16

        132
      • 7.3.2 Special Control Register: Register 17

        133
      • 7.3.3 Clock Synthesis Test and Control Register: Register 18

        134
      • 7.3.4 100BASE-TX Receive False Carrier Counter: Register 19

        134
      • 7.3.5 100Base-TX Receive Disconnect Counter: Register 20

        134
      • 7.3.6 100BASE-TX Receive Error Frame Counter: Register 21

        135
      • 7.3.7 Receive Symbol Error Counter: Register 22

        135
      • 7.3.8 100BASE-TX Receive EOF Error Counter: Register 23

        135
      • 7.3.9 10BASE-T Receive EOF Error Counter: Register 24

        135
      • 7.3.10 10BASE-T Transmit Jabber Detect Counter: Register 25

        135
      • 7.3.11 Equalizer Control and Status Register: Register 26

        136
      • 7.3.12 Special Control Register: Register 27

        137
        • Table 63. LED Switch Control

          138
    • 7.4 Auto-Negotiation Functionality

      138
      • 7.4.1 Description

        138
        • Table 64. Technology Ability Field Bit Assignments

          139
        • Table 65. Technology Priority

          139
      • 7.4.2 Parallel Detection

        139
    • 7.5 Vendor-Specific PHY Programming

      140
      • 7.5.1 Intel 82555 TX PHY

        140
      • 7.5.2 82558 and 82559 Embedded PHY Unit

        140
        • 7.5.2.1 PHY Stand Alone (PHYSA) Mode

          141
  • Programming Recommendations 8

    143
    • 8.1 Adapter Initialization

      143
      • 8.1.1 8255x Initialization

        143
      • 8.1.2 PHY Detection and Initialization

        143
      • 8.1.3 NOS Specific Initialization

        144
    • 8.2 Transmit Processing

      144
    • 8.3 Frame Reception

      144
    • 8.4 Interrupt Processing

      145
  • Wake-up Functionality A

    147
    • A.1 Wake-up Capability

      147
    • A.2 Low Power Modes

      148
    • A.3 Power Management Context After Reset

      148
      • A.3.1 Auxiliary Power Support

        149
      • A.3.2 Auxiliary Power Non-support

        149
    • A.4 Fixed Packet Filtering

      149
      • A.4.1 Magic Packet*

        150
      • A.4.2 Address Matching

        150
      • A.4.3 ARP Packet Filtering

        150
      • A.4.4 Configuration Bits for Fixed Wake-up filters

        151
        • Table 66. Fixed Wake-up Configuration Bits

          151
    • A.5 Link Status Event

      152
    • A.6 Flexible Packet Filtering

      152
      • A.6.1 Flexible Filtering Terminology

        153
      • A.6.2 Flexible Filtering Limitations

        153
      • A.6.3 Wake-up Packet Storage

        154
    • A.7 82559 and Later Generation Device Implementation

      154
      • A.7.1 Load Programmable Filter Command Structures

        154
        • Figure 27. Command Block Structure

          154
          • Example 5. 82559 Wake-up Programming

            156
      • A.7.2 CRC Word calculation of a Flexible Filter

        158
      • A.7.3 Port Dump Wake Up Packet

        158
        • Table 67. 82559 Port Commands

          158
        • Table 68. Dump Data Structure

          159
      • A.7.4 Power Management Software Flow

        159
        • A.7.4.1 Power Down without Wake-up Capabilities

          159
        • A.7.4.2 Power Down with Wake-up Capabilities

          160
        • A.7.4.3 Wake-up Sequence

          160
        • A.7.4.4 Dummy Wake-up Sequence

          161
  • 82550 and 82551QM Specific Information B

    163
    • B.1 IPCB

      163
      • Table 69. IPCB Structure

        163
      • Table 70. IP Activation Bits (Byte 13)

        163
      • Table 71. IP Activation Bits (Byte 12)

        163
      • Table 72. IPCB Fields

        164
      • B.1.1 Maximum TCP Payload / TBD Number and Transmit Threshold

        165
    • B.2 82550 Checksum Operation

      166
      • B.2.1 Driver Interface

        166
        • Table 73. IPCB Structure Checksum Offload

          166
      • B.2.2 IPCB Field Assignment

        167
        • B.2.2.1 Parameters

          167
        • B.2.2.2 Status

          168
        • B.2.2.3 Configuration

          168
      • B.2.3 Data Flow

        168
      • B.2.4 Tunneling Support

        169
    • B.3 Large Send

      169
      • B.3.1 Rationale

        169
      • B.3.2 Driver interface

        169
        • Table 74. IPCB Structure Large Send

          170
      • B.3.3 IPCB Large Send

        170
        • B.3.3.1 Parameters

          170
      • B.3.4 Data Flow

        171
        • B.3.4.1 Headers Parsing

          171
        • B.3.4.2 First Frame Processing

          171
        • B.3.4.3 Intermediate Frames Processing

          172
        • B.3.4.4 Handling the Last Frame

          173
        • B.3.4.5 Performance Considerations

          174
      • B.3.5 Features Co-existence

        174
        • B.3.5.1 Large Send and Checksum

          174
        • B.3.5.2 Large Send and Software Parsing

          174
        • B.3.5.3 Large Send and Scheduling Assist

          174
    • B.4 RCV Checksum Processing

      174
      • B.4.1 Data Flow

        174
        • B.4.1.1 Frame Types

          175
        • B.4.1.2 Verification Types

          175
      • B.4.2 82559 Compatibility

        175
    • B.5 VLAN Tagging

      175