Intel 9110N マニュアル

目次

• Intel® Itanium® Processor 9300 Series

  1
• 1 Introduction

  9
  • 1.1 Overview

    9
  • 1.2 Processor Abstraction Layer

    9
  • 1.3 Mixing Processors of Different Frequencies and Cache Sizes

    10
  • 1.4 Terminology

    10
  • 1.5 State of Data

    10
  • 1.6 Reference Documents

    11
• 2 Electrical Specifications

  13
  • 2.1 Intel® QuickPath Interconnect and Intel® Scalable Memory Interconnect Differential Signaling

    13
  • 2.2 Signal Groups

    14
  • 2.3 Reference Clocking Specifications

    16
  • 2.4 Intel QuickPath Interconnect and Intel SMI Signaling Specifications

    17
    • 2.4.1 Intel QuickPath Interconnect and Intel SMI Specifications for 4.8 GT/s

      17
  • 2.5 Processor Absolute Maximum Ratings

    22
  • 2.6 Processor DC Specifications

    23
    • 2.6.1 Flexible Motherboard Guidelines

      23
    • 2.6.2 Uncore, Core and Cache Tolerances

      26
    • 2.6.3 Overshoot and Undershoot Guidelines

      31
    • 2.6.4 Signal DC Specifications

      32
    • 2.6.5 Motherboard-Socket Specification for VR Sense Point

      34
  • 2.7 Core and Uncore Voltage Identification

    35
  • 2.8 Cache Voltage Identification

    37
  • 2.9 RSVD, Unused, and DEBUG Pins

    38
  • 2.10 Mixing Processors

    38
  • 2.11 Preferred Power-up Voltage Sequence

    38
  • 2.12 Preferred Power-down Voltage Sequence

    39
  • 2.13 Test Access Port (TAP) Connection

    39
• 3 Pin Listing

  41
  • 3.1 Processor Package Bottom Pin Assignments

    41
    • 3.1.1 Package Bottom Pin Listing by Pin Name

      41
    • 3.1.2 Pin Listing by Pin Number

      58
  • 3.2 Processor Package Top Pin Assignments

    75
    • 3.2.1 Top-Side J1 Connector Two-Dimensional Table

      75
    • 3.2.2 Top-Side J2 Connector Two-Dimensional Table

      76
    • 3.2.3 Top-Side J3 Connector Two-Dimensional Table

      78
    • 3.2.4 Top-Side J4 Connector Two-Dimensional Table

      79
• 4 Mechanical Specifications

  81
  • 4.1 Package Mechanical Drawing

    82
  • 4.2 Processor Component Keepout Zones

    87
  • 4.3 Package Loading Specifications

    87
  • 4.4 Package Handling Guidelines

    87
  • 4.5 Processor Mass Specifications

    88
  • 4.6 Processor Materials

    88
  • 4.7 Package Markings

    88
• 5 Thermal Specifications

  91
  • 5.1 Intel Itanium Processor 9300 Series Thermal Features

    91
    • 5.1.1 Digital Thermometer

      91
    • 5.1.2 Intel Itanium Processor 9300 Series Thermal Management

      92
    • 5.1.3 Thermal Alert

      93
    • 5.1.4 TCONTROL

      93
    • 5.1.5 Thermal Warning

      94
    • 5.1.6 Thermal Trip

      94
    • 5.1.7 PROCHOT

      94
    • 5.1.8 FORCEPR_N Signal Pin

      95
    • 5.1.9 Ararat Voltage Regulator Thermal Signals

      95
  • 5.2 Package Thermal Specifications and Considerations

    95
  • 5.3 Storage Conditions Specifications

    96
• 6 System Management Bus Interface

  99
  • 6.1 Introduction

    99
  • 6.2 SMBus Memory Component

    99
    • 6.2.1 Processor Information ROM

      99
    • 6.2.2 Scratch EEPROM

      104
    • 6.2.3 PIROM and Scratch EEPROM Supported SMBus Transactions

      104
  • 6.3 Memory Component Addressing

    105
  • 6.4 PIROM Field Definitions

    106
    • 6.4.1 General

      106
    • 6.4.2 Processor Data

      106
    • 6.4.3 Processor Core Data

      106
    • 6.4.4 Processor Uncore Data

      107
    • 6.4.5 Cache Data

      108
    • 6.4.6 Package Data

      108
    • 6.4.7 Part Number Data

      108
    • 6.4.8 Thermal Reference Data

      109
    • 6.4.9 Feature Data

      109
    • 6.4.10 Other Data

      110
    • 6.4.11 Checksums

      110
• 7 Intel Itanium Processor 9300 Series Signal Definitions

  113