Intel BX80525KY500512 マニュアル

目次

• Introduction

  9
• Terminology

  9
• Introduction

  9
• Terminology

  9
• 1.1.1 S.E.C. Cartridge Terminology

  10
• References

  10
• 1.1.1 S.E.C. Cartridge Terminology

  10
• References

  10
• Electrical Specifications

  11
• The Pentium® III Xeon™ Processor System Bus and VREF

  11
• Electrical Specifications

  11
• The Pentium® III Xeon™ Processor System Bus and VREF

  11
• Power and Ground Pins

  12
• Decoupling Guidelines

  12
• Power and Ground Pins

  12
• Decoupling Guidelines

  12
• 2.3.1 Pentium® III Xeon™ Processor VCCCORE

  13
• 2.3.2 Level 2 Cache Decoupling

  13
• 2.3.3 System Bus AGTL+ Decoupling

  13
• System Bus Clock and Processor Clocking

  13
• 2.3.1 Pentium® III Xeon™ Processor VCCCOR

  13
• 2.3.2 Level 2 Cache Decoupling

  13
• 2.3.3 System Bus AGTL+ Decoupling

  13
• System Bus Clock and Processor Clocking

  13
• Core Frequency to System Bus Multiplier Configuration

  14
• Core Frequency to System Bus Multiplier Configuration

  14
• 2.4.1 Mixing Processors

  15
• Timing Diagram of Clock Ratio Signals

  15
• Logical Schematic for Clock Ratio Pin Sharing

  15
• 2.4.1 Mixing Processors

  15
• Timing Diagram of Clock Ratio Signals

  15
• Logical Schematic for Clock Ratio Pin Sharing

  15
• Voltage Identification

  16
• Core and L2 Voltage Identification Definition

  16
• Voltage Identification

  16
• Core and L2 Voltage Identification Definition 1, 2

  16
• System Bus Unused Pins and Test Pins

  17
• System Bus Unused Pins and Test Pins

  17
• System Bus Signal Groups

  18
• Pentium® III Xeon™ Processor System Bus Pin Groups

  18
• System Bus Signal Groups

  18
• Pentium® III Xeon™ Processor System Bus Pin Groups

  18
• 2.7.1 Asynchronous vs. Synchronous for System Bus Signals

  19
• Test Access Port (TAP) Connection

  19
• 2.7.1 Asynchronous vs. Synchronous for System Bus Signals

  19
• Test Access Port (TAP) Connection

  19
• Maximum Ratings

  20
• Processor DC Specifications

  20
• Pentium® III Xeon™ Processor Absolute Maximum Ratings

  20
• Maximum Ratings

  20
• Processor DC Specifications

  20
• Pentium® III Xeon™ Processor Absolute Maximum Ratings

  20
• Voltage Specifications

  21
• Voltage Specifications 1

  21
• Current Specifications

  22
• Current Specifications 1

  22
• I-V Curve for nMOS Device

  23
• AGTL+ Signal Groups, DC Specifications at the Processor Core

  23
• I-V Curve for nMOS Device

  23
• AGTL+ Signal Groups, DC Specifications at the Processor Core

  23
• AGTL+ System Bus Specifications

  24
• Processor Core

  24
• SMBus Signal Group, DC Specifications at the Processor Core

  24
• AGTL+ System Bus Specifications

  24
• SMBus Signal Group, DC Specifications at the Processor Core

  24
• System Bus AC Specifications

  25
• Pentium® III Xeon™ Processor Internal Parameters for the AGTL+ Bus

  25
• System Bus AC Specifications (Clock) at the Processor Core

  25
• System Bus AC Specifications

  25
• Pentium® III Xeon™ Processor Internal Parameters for the AGTL+ Bus

  25
• System Bus AC Specifications (Clock) at the Processor Core

  25
• Processor Core

  26
• System Bus AC Specifications (Reset Conditions)

  27
• Core

  27
• System Bus AC Specifications (Reset Conditions)

  27
• System Bus AC Specifications (TAP Connection) at the Processor Core

  28
• SMBus Signal Group, AC Specifications at the Edge Fingers

  28
• System Bus AC Specifications (TAP Connection) at the Processor Core 1

  28
• SMBus Signal Group, AC Specifications at the Edge Fingers

  28
• BCLK, PICCLK, TCK Generic Clock Waveform

  29
• SMBCLK Clock Waveform

  29
• Valid Delay Timings

  29
• BCLK, PICCLK, TCK Generic Clock Waveform

  29
• SMBCLK Clock Waveform

  29
• Valid Delay Timings

  29
• Setup and Hold Timings

  30
• FRC Mode BCLK to PICCLK Timing

  30
• Setup and Hold Timings

  30
• FRC Mode BCLK to PICCLK Timing

  30
• System Bus Reset and Configuration Timings

  31
• Power-On Reset and Configuration Timings

  31
• System Bus Reset and Configuration Timings

  31
• Power-On Reset and Configuration Timings

  31
• Signal Quality

  32
• Test Timings (Boundary Scan)

  32
• Test Reset Timings

  32
• Signal Quality

  32
• Test Timings (Boundary Scan)

  32
• Test Reset Timings

  32
• System Bus Clock Signal Quality Specifications

  33
• AGTL+ Signal Quality Specifications

  33
• BCLK, TCK, PICCLK Generic Clock Waveform at the Processor Core Pins

  33
• BCLK Signal Quality Specifications for Simulation at the Processor Core

  33
• System Bus Clock Signal Quality Specifications

  33
• AGTL+ Signal Quality Specifications

  33
• BCLK, TCK, PICCLK Generic Clock Waveform at the Processor Core Pins

  33
• BCLK Signal Quality Specifications for Simulation at the Processor Core 1

  33
• 3.2.1 AGTL+ Ringback Tolerance Specifications

  34
• 3.2.2 AGTL+ Overshoot/Undershoot Guidelines

  34
• Low to High AGTL+ Receiver Ringback Tolerance

  34
• Core

  34
• 3.2.1 AGTL+ Ringback Tolerance Specifications

  34
• 3.2.2 AGTL+ Overshoot/Undershoot Guidelines

  34
• Low to High AGTL+ Receiver Ringback Tolerance

  34
• Non-AGTL+ Signal Quality Specifications

  35
• 3.3.1 2.5 V Tolerant Buffer Overshoot/Undershoot Guidelines

  35
• 3.3.2 2.5 V Tolerant Buffer Ringback Specification

  35
• Non-AGTL+ Overshoot/Undershoot, Settling Limit, and Ringback

  35
• AGTL+ Overshoot/Undershoot Guidelines at the Processor Core

  35
• Non-AGTL+ Signal Quality Specifications

  35
• 3.3.1 2.5 V Tolerant Buffer Overshoot/Undershoot Guidelines

  35
• 3.3.2 2.5 V Tolerant Buffer Ringback Specification

  35
• Non-AGTL+ Overshoot/Undershoot, Settling Limit, and Ringback

  35
• AGTL+ Overshoot/Undershoot Guidelines at the Processor Core

  35
• 3.3.3 2.5 V Tolerant Buffer Settling Limit Guideline

  36
• Processor Features

  36
• Functional Redundancy Checking Mode

  36
• Processor Core

  36
• 3.3.3 2.5 V Tolerant Buffer Settling Limit Guideline

  36
• Processor Features

  36
• Functional Redundancy Checking Mode

  36
• Low Power States and Clock Control

  37
• 4.2.1 Normal State— State 1

  37
• 4.2.2 Auto Halt Power Down State — State 2

  37
• Low Power States and Clock Control

  37
• 4.2.1 Normal State— State 1

  37
• 4.2.2 Auto Halt Power Down State — State 2

  37
• 4.2.3 Stop-Grant State — State 3

  38
• Stop Clock State Machine

  38
• 4.2.3 Stop-Grant State — State 3

  38
• Stop Clock State Machine

  38
• 4.2.4 Halt/Grant Snoop State — State 4

  39
• 4.2.5 Sleep State — State 5

  39
• 4.2.6 Clock Control

  39
• 4.2.4 Halt/Grant Snoop State — State 4

  39
• 4.2.5 Sleep State — State 5

  39
• 4.2.6 Clock Control

  39
• System Management Bus (SMBus) Interface

  40
• Logical Schematic of SMBus Circuitry

  40
• System Management Bus (SMBus) Interface

  40
• Logical Schematic of SMBus Circuitry

  40
• 4.3.1 Processor Information ROM

  41
• Processor Information ROM Format

  41
• 4.3.1 Processor Information ROM

  41
• Processor Information ROM Format

  41
• 4.3.2 Scratch EEPROM

  42
• 4.3.2 Scratch EEPROM

  42
• SMBus Transactions

  43
• Thermal Sensor

  43
• Current Address Read SMBus Packet

  43
• Random Address Read SMBus Packet

  43
• Byte Write SMBus Packet

  43
• 4.3.4 Thermal Sensor

  43
• Current Address Read SMBus Packet

  43
• Random Address Read SMBus Packet

  43
• Byte Write SMBus Packet

  43
• Thermal Sensor Supported SMBus Transactions

  44
• 4.3.5 Thermal Sensor Supported SMBus Transactions

  44
• Write Byte SMBus Packet

  45
• Read Byte SMBus Packet

  45
• Send Byte SMBus Packet

  45
• Receive Byte SMBus Packet

  45
• ARA SMBus Packet

  45
• Command Byte Bit Assignments

  45
• Write Byte SMBus Packet

  45
• Read Byte SMBus Packet

  45
• Send Byte SMBus Packet

  45
• Receive Byte SMBus Packet

  45
• ARA SMBus Packet

  45
• Command Byte Bit Assignments

  45
• Thermal Sensor Registers

  46
• 4.3.6.1 Thermal Reference Registers

  46
• 4.3.6.2 Thermal Limit Registers

  46
• 4.3.6.3 Status Register

  46
• 4.3.6 Thermal Sensor Registers

  46
• 4.3.6.1 Thermal Reference Registers

  46
• 4.3.6.2 Thermal Limit Registers

  46
• 4.3.6.3 Status Register

  46
• 4.3.6.4 Configuration Register

  47
• 4.3.6.5 Conversion Rate Register

  47
• Thermal Sensor Status Register

  47
• Thermal Sensor Configuration Register

  47
• 4.3.6.4 Configuration Register

  47
• 4.3.6.5 Conversion Rate Register

  47
• Thermal Sensor Status Register

  47
• Thermal Sensor Configuration Register

  47
• SMBus Device Addressing

  48
• Thermal Sensor Conversion Rate Register

  48
• SMBus Device Addressing

  48
• Thermal Sensor Conversion Rate Register

  48
• Thermal Specifications and Design Considerations

  49
• Thermal Sensor SMBus Addressing on the Pentium® III Xeon™ Processor

  49
• Memory Device SMBus Addressing on the Pentium® III Xeon™ Processor

  49
• Thermal Specifications and Design Considerations

  49
• Thermal Sensor SMBus Addressing on the Pentium® III Xeon™ Processor

  49
• Memory Device SMBus Addressing on the Pentium® III Xeon™ Processor

  49
• Thermal Specifications

  50
• 5.1.1 Power Dissipation

  50
• Thermal Plate View

  50
• Thermal Specifications

  50
• 5.1.1 Power Dissipation

  50
• Thermal Plate View

  50
• 5.1.2 Plate Flatness Specification

  51
• Processor Thermal Analysis

  51
• 5.2.1 Thermal Solution Performance

  51
• Plate Flatness Reference

  51
• Thermal Design Power

  51
• 5.1.2 Plate Flatness Specification

  51
• Processor Thermal Analysis

  51
• 5.2.1 Thermal Solution Performance

  51
• Plate Flatness Reference

  51
• Thermal Design Power 1

  51
• 5.2.2 Thermal Plate to Heat Sink Interface Management Guide

  52
• 5.2.2 Thermal Plate to Heat Sink Interface Management Guide

  52
• 5.2.3 Measurements for Thermal Specifications

  53
• 5.2.3.1 Thermal Plate Temperature Measurement

  53
• Measurement Points

  53
• 5.2.3 Measurements for Thermal Specifications

  53
• 5.2.3.1 Thermal Plate Temperature Measurement

  53
• 5.2.3.2 Cover Temperature Measurement Guideline

  54
• Technique for Measuring TPLATE with 0° Angle Attachment

  54
• Technique for Measuring TPLATE with 90° Angle Attachment

  54
• 5.2.3.2 Cover Temperature Measurement Guideline

  54
• Technique for Measuring TPLATE with 0° Angle Attachment

  54
• Technique for Measuring TPLATE with 90° Angle Attachment

  54
• Mechanical Specifications

  55
• Placement

  55
• Mechanical Specifications

  55
• Isometric View of Pentium® III Xeon™ Processor S.E.C. Cartridge

  56
• Isometric View of Pentium® III Xeon™ Processor S.E.C. Cartridge

  56
• S.E.C. Cartridge Cooling Solution Attach Details (Notes follow Figure 27)

  57
• S.E.C. Cartridge Cooling Solution Attach Details (Notes follow Figure 27)

  57
• S.E.C. Cartridge Retention Enabling Details (Notes follow Figure 27)

  58
• S.E.C. Cartridge Retention Enabling Details (Notes follow Figure 27)

  58
• S.E.C. Cartridge Retention Enabling Details

  59
• S.E.C. Cartridge Retention Enabling Details

  59
• Weight

  60
• Cartridge to Connector Mating Details

  60
• Side View of Connector Mating Details

  60
• Weight

  60
• Cartridge to Connector Mating Details

  60
• Side View of Connector Mating Details

  60
• Top View of Cartridge Insertion Pressure Points

  61
• Front View of Connector Mating Details

  61
• Top View of Cartridge Insertion Pressure Points

  61
• Front View of Connector Mating Details

  61
• Pentium® III Xeon™ Processor Substrate Edge Finger Signal Listing

  62
• Signal Listing in Order by Pin Number

  62
• Pentium® III Xeon™ Processor Substrate Edge Finger Signal Listing

  62
• Signal Listing in Order by Pin Number

  62
• Signal Listing in Order by Pin Name

  66
• Signal Listing in Order by Pin Name

  66
• Boxed Processor Specifications

  71
• Introduction

  71
• Mechanical Specifications

  71
• Boxed Pentium® III Xeon™ Processor

  71
• Boxed Processor Specifications

  71
• Introduction

  71
• Mechanical Specifications

  71
• Boxed Pentium® III Xeon™ Processor

  71
• Side View Space Requirements for the Boxed Processor

  72
• Side View Space Requirements for the Boxed Processor

  72
• 7.2.1 Boxed Processor Heatsink Dimensions

  73
• 7.2.2 Boxed Processor Heatsink Weight

  73
• 7.2.3 Boxed Processor Retention Mechanism

  73
• Front View Space Requirements for the Boxed Processor

  73
• Boxed Processor Heatsink Dimensions

  73
• 7.2.1 Boxed Processor Heatsink Dimensions

  73
• 7.2.2 Boxed Processor Heatsink Weight

  73
• 7.2.3 Boxed Processor Retention Mechanism

  73
• Front View Space Requirements for the Boxed Processor

  73
• Boxed Processor Heatsink Dimensions

  73
• Thermal Specifications

  74
• 7.3.1 Boxed Processor Cooling Requirements

  74
• 7.3.2 Optional Auxiliary Fan Attachment

  74
• Thermal Specifications

  74
• 7.3.1 Boxed Processor Cooling Requirements

  74
• 7.3.2 Optional Auxiliary Fan Attachment

  74
• (Not Included with Boxed Processor)

  75
• (Fan Not Included)

  75
• 7.3.2.1 Clearance Recommendations for Auxiliary Fan

  76
• (Grommet Shown)

  76
• Side View Space Recommendation for the Auxiliary Fan

  76
• 7.3.2.1 Clearance Recommendations for Auxiliary Fan

  76
• Side View Space Recommendation for the Auxiliary Fan

  76
• 7.3.2.2 Fan Power Recommendations for Auxiliary Fan

  77
• Front View Space Recommendations for the Auxiliary Fan

  77
• Boxed Processor Fan/Heatsink Power Cable Connector Description

  77
• 7.3.2.2 Fan Power Recommendations for Auxiliary Fan

  77
• Front View Space Recommendations for the Auxiliary Fan

  77
• Boxed Processor Fan/Heatsink Power Cable Connector Description

  77
• 7.3.2.3 Thermal Evaluation for Auxiliary Fan

  78
• Integration Tools

  78
• In-Target Probe (ITP) for Pentium® III Xeon™ Processors

  78
• Fan/Heatsink Power and Signal Specifications

  78
• 7.3.2.3 Thermal Evaluation for Auxiliary Fan

  78
• Integration Tools

  78
• In-Target Probe (ITP) for Pentium® III Xeon™ Processors

  78
• Fan/Heatsink Power and Signal Specifications

  78
• 8.1.1 Primary Function

  79
• 8.1.2 Debug Port Connector Description

  79
• Hardware Components of an ITP

  79
• 8.1.1 Primary Function

  79
• 8.1.2 Debug Port Connector Description

  79
• Hardware Components of an ITP

  79
• 8.1.3 Debug Port Signal Descriptions

  80
• Debug Port Pinout Description and Requirements

  80
• 8.1.3 Debug Port Signal Descriptions

  80
• Debug Port Pinout Description and Requirements 1

  80
• 8.1.4 Debug Port Signal Notes

  82
• AGTL+ Signal Termination

  82
• 8.1.4 Debug Port Signal Notes

  82
• AGTL+ Signal Termination

  82
• 8.1.4.1 General Signal Quality Notes

  83
• 8.1.4.2 Signal Note: DBRESET#

  83
• 8.1.4.3 Signal Note: TDO and TDI

  83
• 8.1.4.4 Signal Note: TCK

  83
• 8.1.4.1 General Signal Quality Notes

  83
• 8.1.4.2 Signal Note: DBRESET#

  83
• 8.1.4.3 Signal Note: TDO and TDI

  83
• 8.1.4.4 Signal Note: TCK

  83
• TCK with Individual Buffering Scheme

  84
• TCK with Individual Buffering Scheme

  84
• 8.1.5 Using Boundary Scan to Communicate to the Processor

  85
• System Preferred Debug Port Layout

  85
• 8.1.5 Using Boundary Scan to Communicate to the Processor

  85
• System Preferred Debug Port Layout

  85
• Integration Tool (Logic Analyzer) Considerations

  86
• Appendix

  86
• Alphabetical Signals Reference

  86
• 9.1.1 A[35:03]# (I/O)

  86
• 9.1.2 A20M# (I)

  86
• Integration Tool (Logic Analyzer) Considerations

  86
• Appendix

  86
• Alphabetical Signals Reference

  86
• 9.1.1 A[35:03]# (I/O)

  86
• A20M# (I)

  86
• 9.1.3 ADS# (I/O)

  87
• 9.1.4 AERR# (I/O)

  87
• 9.1.5 AP[1:0]# (I/O)

  87
• 9.1.6 BCLK (I)

  87
• 9.1.7 BERR# (I/O)

  87
• ADS# (I/O)

  87
• AERR# (I/O)

  87
• AP[1:0]# (I/O)

  87
• BCLK (I)

  87
• BERR# (I/O)

  87
• 9.1.8 BINIT# (I/O)

  88
• 9.1.9 BNR# (I/O)

  88
• 9.1.10 BP[3:2]# (I/O)

  88
• 9.1.11 BPM[1:0]# (I/O)

  88
• 9.1.12 BPRI# (I)

  88
• 9.1.13 BR0# (I/O), BR[3:1]# (I)

  88
• BINIT# (I/O)

  88
• BNR# (I/O)

  88
• BP[3:2]# (I/O)

  88
• BPM[1:0]# (I/O)

  88
• BPRI# (I)

  88
• BR0# (I/O), BR[3:1]# (I)

  88
• 9.1.14 CPU_SENSE

  89
• 9.1.15 D[63:00]# (I/O)

  89
• BR[3:0]# Signals Rotating Interconnect, 4-Way System

  89
• BR[3:0]# Signals Rotating Interconnect, 2-Way System

  89
• Agent ID Configuration

  89
• CPU_SENSE

  89
• D[63:00]# (I/O)

  89
• BR[3:0]# Signals Rotating Interconnect, 4-Way System

  89
• BR[3:0]# Signals Rotating Interconnect, 2-Way System

  89
• Agent ID Configuration

  89
• 9.1.16 DBSY# (I/O)

  90
• 9.1.17 DEFER# (I)

  90
• 9.1.18 DEP[7:0]# (I/O)

  90
• 9.1.19 DRDY# (I/O)

  90
• 9.1.20 EMI

  90
• 9.1.21 FERR# (O)

  90
• 9.1.22 FLUSH# (I)

  90
• DBSY# (I/O)

  90
• DEFER# (I)

  90
• DEP[7:0]# (I/O)

  90
• DRDY# (I/O)

  90
• EMI

  90
• FERR# (O)

  90
• FLUSH# (I)

  90
• 9.1.23 FRCERR (I/O)

  91
• 9.1.24 HIT# (I/O), HITM# (I/O)

  91
• 9.1.25 IERR# (O)

  91
• 9.1.26 IGNNE# (I)

  91
• FRCERR (I/O)

  91
• HIT# (I/O), HITM# (I/O)

  91
• IERR# (O)

  91
• IGNNE# (I)

  91
• 9.1.27 INIT# (I)

  92
• 9.1.28 INTR - see LINT0

  92
• 9.1.29 LINT[1:0] (I)

  92
• 9.1.30 LOCK# (I/O)

  92
• INIT# (I)

  92
• INTR - see LINT0

  92
• LINT[1:0] (I)

  92
• LOCK# (I/O)

  92
• 9.1.31 L2_SENSE

  93
• 9.1.32 NMI - See LINT1

  93
• 9.1.33 PICCLK (I)

  93
• 9.1.34 PICD[1:0] (I/O)

  93
• 9.1.35 PM[1:0]# (O)

  93
• 9.1.36 PRDY# (O)

  93
• 9.1.37 PREQ# (I)

  93
• 9.1.38 PWREN[1:0] (I)

  93
• 9.1.39 PWRGOOD (I)

  93
• L2_SENSE

  93
• NMI - See LINT1

  93
• PICCLK (I)

  93
• PICD[1:0] (I/O)

  93
• PM[1:0]# (O)

  93
• PRDY# (O)

  93
• PREQ# (I)

  93
• PWREN[1:0] (I)

  93
• PWRGOOD (I)

  93
• 9.1.40 REQ[4:0]# (I/O)

  94
• 9.1.41 RESET# (I)

  94
• PWRGOOD Relationship at Power-On

  94
• REQ[4:0]# (I/O)

  94
• RESET# (I)

  94
• PWRGOOD Relationship at Power-On

  94
• 9.1.42 RP# (I/O)

  95
• 9.1.43 RS[2:0]# (I)

  95
• 9.1.44 RSP# (I)

  95
• 9.1.45 SA[2:0] (I)

  95
• RP# (I/O)

  95
• RS[2:0]# (I)

  95
• RSP# (I)

  95
• SA[2:0] (I)

  95
• 9.1.46 SELFSB[1:0] (I/O)

  96
• 9.1.47 SLP# (I)

  96
• 9.1.48 SMBALERT# (O)

  96
• 9.1.49 SMBCLK (I)

  96
• 9.1.50 SMBDAT (I/O)

  96
• 9.1.51 SMI# (I)

  96
• SELFSB[1:0] (I/O)

  96
• SLP# (I)

  96
• SMBALERT# (O)

  96
• SMBCLK (I)

  96
• SMBDAT (I/O)

  96
• SMI# (I)

  96
• 9.1.52 STPCLK# (I)

  97
• 9.1.53 TCK (I)

  97
• 9.1.54 TDI (I)

  97
• 9.1.55 TDO (O)

  97
• 9.1.56 TEST_25_A62 (I)

  97
• 9.1.57 TEST_VCC_CORE_XXX (I)

  97
• 9.1.58 THERMTRIP# (O)

  97
• 9.1.52 STPCLK# (I)

  97
• 9.1.53 TCK (I)

  97
• 9.1.54 TDI (I)

  97
• 9.1.55 TDO (O)

  97
• 9.1.56 TEST_25_A62 (I)

  97
• 9.1.57 TEST_VCC_CORE_XXX (I)

  97
• 9.1.58 THERMTRIP# (O)

  97
• 9.1.59 TMS (I)

  98
• 9.1.60 TRDY# (I)

  98
• 9.1.61 TRST# (I)

  98
• 9.1.62 VID_L2[4:0], VID_CORE[4:0](O)

  98
• 9.1.63 WP (I)

  98
• Signal Summaries

  98
• Output Signals

  98
• 9.1.59 TMS (I)

  98
• 9.1.60 TRDY# (I)

  98
• 9.1.61 TRST# (I)

  98
• 9.1.62 VID_L2[4:0], VID_CORE[4:0](O)

  98
• 9.1.63 WP (I)

  98
• Signal Summaries

  98
• Output Signals †

  98
• Input Signals1

  99
• Input Signals 1

  99
• I/O Signals (Single Driver)

  100
• I/O Signals (Multiple Driver)

  100
• I/O Signals (Single Driver)

  100
• I/O Signals (Multiple Driver)

  100