Intel Celeron M 520 1.60 GHz マニュアル

目次

• 1 Introduction

  7
  • 1.1 Terminology

    8
  • 1.2 References

    9
  • 1.3 State of Data

    9
• 2 Low Power Features

  11
  • 2.1 Clock Control and Low Power States

    11
    • 2.1.1 Normal State

      11
    • 2.1.2 AutoHALT Power-Down State

      11
    • 2.1.3 Stop-Grant State

      12
    • 2.1.4 HALT/Grant Snoop State

      12
    • 2.1.5 Sleep State

      12
    • 2.1.6 Deep Sleep State

      13
  • 2.2 FSB Low Power Enhancements

    13
  • 2.3 Processor Power Status Indicator (PSI#) Signal

    14
• 3 Electrical Specifications

  15
  • 3.1 FSB and GTLREF

    15
  • 3.2 Power and Ground Pins

    15
  • 3.3 Decoupling Guidelines

    15
    • 3.3.1 VCC Decoupling

      16
    • 3.3.2 FSB AGTL+ Decoupling

      16
    • 3.3.3 FSB Clock (BCLK[1:0]) and Processor Clocking

      16
  • 3.4 Voltage Identification

    16
  • 3.5 Catastrophic Thermal Protection

    17
  • 3.6 Signal Terminations and Unused Pins

    18
  • 3.7 FSB Signal Groups

    18
  • 3.8 CMOS Signals

    19
  • 3.9 Maximum Ratings

    20
  • 3.10 Processor DC Specifications

    20
• 4 Package Mechanical Specifications and Pin Information

  29
  • 4.1 Processor Pin-Out and Pin List

    37
  • 4.2 Alphabetical Signals Reference

    56
• 5 Thermal Specifications and Design Considerations

  63
  • 5.1 Thermal Specifications

    65
    • 5.1.1 Thermal Diode

      65
    • 5.1.2 Intel Thermal Monitor

      66
• 6 Debug Tools Specifications

  69
  • 6.1 Logic Analyzer Interface (LAI)

    69
    • 6.1.1 Mechanical Considerations

      69
    • 6.1.2 Electrical Considerations

      69