ユーザーズマニュアル (CM8064601481914)目次Contents3Revision History81.0 Introduction91.1 Supported Technologies101.2 Interfaces111.3 Power Management Support111.4 Thermal Management Support121.5 Package Support121.6 Terminology121.7 Related Documents152.0 Interfaces172.1 System Memory Interface172.1.1 System Memory Technology Supported182.1.2 System Memory Timing Support192.1.3 System Memory Organization Modes192.1.3.1 System Memory Frequency212.1.3.2 Intel® Fast Memory Access (Intel® FMA) Technology Enhancements212.1.3.3 Data Scrambling212.2 PCI Express* Interface222.2.1 PCI Express* Support222.2.2 PCI Express* Architecture232.2.3 PCI Express* Configuration Mechanism232.3 Direct Media Interface (DMI)252.4 Processor Graphics272.5 Processor Graphics Controller (GT)272.5.1 3D and Video Engines for Graphics Processing282.5.2 Multi Graphics Controllers Multi-Monitor Support302.6 Digital Display Interface (DDI)302.7 Intel® Flexible Display Interface (Intel® FDI)362.8 Platform Environmental Control Interface (PECI)362.8.1 PECI Bus Architecture363.0 Technologies383.1 Intel® Virtualization Technology (Intel® VT)383.2 Intel® Trusted Execution Technology (Intel® TXT)423.3 Intel® Hyper-Threading Technology (Intel® HT Technology)433.4 Intel® Turbo Boost Technology443.5 Intel® Advanced Vector Extensions 2.0 (Intel® AVX2)443.6 Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI)453.7 Intel® Transactional Synchronization Extensions (Intel® TSX)453.8 Intel® 64 Architecture x2APIC463.9 Power Aware Interrupt Routing (PAIR)473.10 Execute Disable Bit473.11 Supervisor Mode Execution Protection (SMEP)474.0 Power Management484.1 Advanced Configuration and Power Interface (ACPI) States Supported494.2 Processor Core Power Management504.2.1 Enhanced Intel® SpeedStep® Technology Key Features504.2.2 Low-Power Idle States514.2.3 Requesting Low-Power Idle States524.2.4 Core C-State Rules534.2.5 Package C-States544.3 Integrated Memory Controller (IMC) Power Management584.3.1 Disabling Unused System Memory Outputs584.3.2 DRAM Power Management and Initialization584.3.2.1 Initialization Role of CKE594.3.2.2 Conditional Self-Refresh604.3.2.3 Dynamic Power-Down604.3.2.4 DRAM I/O Power Management604.3.3 DRAM Running Average Power Limitation (RAPL)604.3.4 DDR Electrical Power Gating (EPG)614.4 PCI Express* Power Management614.5 Direct Media Interface (DMI) Power Management614.6 Graphics Power Management614.6.1 Intel® Rapid Memory Power Management (Intel® RMPM)614.6.2 Graphics Render C-State614.6.3 Intel® Graphics Dynamic Frequency615.0 Thermal Management635.1 Thermal Metrology645.2 Fan Speed Control Scheme with Digital Thermal Sensor (DTS) 1.1645.3 Fan Speed Control Scheme with Digital Thermal Sensor (DTS) 2.0665.4 Intel® Xeon® Processor E3-1200 v3 Product Family Thermal Specifications675.5 Processor Temperature695.6 Adaptive Thermal Monitor695.7 THERMTRIP# Signal725.8 Digital Thermal Sensor735.8.1 Digital Thermal Sensor Accuracy (Taccuracy)735.9 Intel® Turbo Boost Technology Thermal Considerations745.9.1 Intel® Turbo Boost Technology Power Control and Reporting745.9.2 Package Power Control755.9.3 Turbo Time Parameter756.0 Signal Description776.1 System Memory Interface Signals776.2 Memory Reference and Compensation796.3 Reset and Miscellaneous Signals806.4 PCI Express*-Based Interface Signals816.5 Display Interface Signals816.6 Direct Media Interface (DMI)826.7 Phase Locked Loop (PLL) Signals826.8 Testability Signals826.9 Error and Thermal Protection Signals836.10 Power Sequencing846.11 Processor Power Signals846.12 Sense Pins846.13 Ground and Non-Critical to Function (NCTF) Signals856.14 Processor Internal Pull-Up / Pull-Down Terminations857.0 Electrical Specifications867.1 Integrated Voltage Regulator867.2 Power and Ground Lands867.3 VCC Voltage Identification (VID)867.4 Reserved or Unused Signals917.5 Signal Groups917.6 Test Access Port (TAP) Connection937.7 DC Specifications937.8 Voltage and Current Specifications947.8.1 PECI DC Characteristics997.8.2 Input Device Hysteresis1008.0 Package Mechanical Specifications1018.1 Processor Component Keep-Out Zone1018.2 Package Loading Specifications1018.3 Package Handling Guidelines1028.4 Package Insertion Specifications1028.5 Processor Mass Specification1028.6 Processor Materials1028.7 Processor Markings1038.8 Processor Land Coordinates1038.9 Processor Storage Specifications1049.0 Processor Ball and Signal Information106サイズ： 2.02MBページ数： 116Language: Englishマニュアルを開く
ユーザーズマニュアル (CM8064601467804)目次Contents3Revision History81.0 Introduction91.1 Supported Technologies101.2 Interfaces111.3 Power Management Support111.4 Thermal Management Support121.5 Package Support121.6 Terminology121.7 Related Documents152.0 Interfaces172.1 System Memory Interface172.1.1 System Memory Technology Supported182.1.2 System Memory Timing Support192.1.3 System Memory Organization Modes192.1.3.1 System Memory Frequency212.1.3.2 Intel® Fast Memory Access (Intel® FMA) Technology Enhancements212.1.3.3 Data Scrambling212.2 PCI Express* Interface222.2.1 PCI Express* Support222.2.2 PCI Express* Architecture232.2.3 PCI Express* Configuration Mechanism232.3 Direct Media Interface (DMI)252.4 Processor Graphics272.5 Processor Graphics Controller (GT)272.5.1 3D and Video Engines for Graphics Processing282.5.2 Multi Graphics Controllers Multi-Monitor Support302.6 Digital Display Interface (DDI)302.7 Intel® Flexible Display Interface (Intel® FDI)362.8 Platform Environmental Control Interface (PECI)362.8.1 PECI Bus Architecture363.0 Technologies383.1 Intel® Virtualization Technology (Intel® VT)383.2 Intel® Trusted Execution Technology (Intel® TXT)423.3 Intel® Hyper-Threading Technology (Intel® HT Technology)433.4 Intel® Turbo Boost Technology443.5 Intel® Advanced Vector Extensions 2.0 (Intel® AVX2)443.6 Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI)453.7 Intel® Transactional Synchronization Extensions (Intel® TSX)453.8 Intel® 64 Architecture x2APIC463.9 Power Aware Interrupt Routing (PAIR)473.10 Execute Disable Bit473.11 Supervisor Mode Execution Protection (SMEP)474.0 Power Management484.1 Advanced Configuration and Power Interface (ACPI) States Supported494.2 Processor Core Power Management504.2.1 Enhanced Intel® SpeedStep® Technology Key Features504.2.2 Low-Power Idle States514.2.3 Requesting Low-Power Idle States524.2.4 Core C-State Rules534.2.5 Package C-States544.3 Integrated Memory Controller (IMC) Power Management584.3.1 Disabling Unused System Memory Outputs584.3.2 DRAM Power Management and Initialization584.3.2.1 Initialization Role of CKE594.3.2.2 Conditional Self-Refresh604.3.2.3 Dynamic Power-Down604.3.2.4 DRAM I/O Power Management604.3.3 DRAM Running Average Power Limitation (RAPL)604.3.4 DDR Electrical Power Gating (EPG)614.4 PCI Express* Power Management614.5 Direct Media Interface (DMI) Power Management614.6 Graphics Power Management614.6.1 Intel® Rapid Memory Power Management (Intel® RMPM)614.6.2 Graphics Render C-State614.6.3 Intel® Graphics Dynamic Frequency615.0 Thermal Management635.1 Thermal Metrology645.2 Fan Speed Control Scheme with Digital Thermal Sensor (DTS) 1.1645.3 Fan Speed Control Scheme with Digital Thermal Sensor (DTS) 2.0665.4 Intel® Xeon® Processor E3-1200 v3 Product Family Thermal Specifications675.5 Processor Temperature695.6 Adaptive Thermal Monitor695.7 THERMTRIP# Signal725.8 Digital Thermal Sensor735.8.1 Digital Thermal Sensor Accuracy (Taccuracy)735.9 Intel® Turbo Boost Technology Thermal Considerations745.9.1 Intel® Turbo Boost Technology Power Control and Reporting745.9.2 Package Power Control755.9.3 Turbo Time Parameter756.0 Signal Description776.1 System Memory Interface Signals776.2 Memory Reference and Compensation796.3 Reset and Miscellaneous Signals806.4 PCI Express*-Based Interface Signals816.5 Display Interface Signals816.6 Direct Media Interface (DMI)826.7 Phase Locked Loop (PLL) Signals826.8 Testability Signals826.9 Error and Thermal Protection Signals836.10 Power Sequencing846.11 Processor Power Signals846.12 Sense Pins846.13 Ground and Non-Critical to Function (NCTF) Signals856.14 Processor Internal Pull-Up / Pull-Down Terminations857.0 Electrical Specifications867.1 Integrated Voltage Regulator867.2 Power and Ground Lands867.3 VCC Voltage Identification (VID)867.4 Reserved or Unused Signals917.5 Signal Groups917.6 Test Access Port (TAP) Connection937.7 DC Specifications937.8 Voltage and Current Specifications947.8.1 PECI DC Characteristics997.8.2 Input Device Hysteresis1008.0 Package Mechanical Specifications1018.1 Processor Component Keep-Out Zone1018.2 Package Loading Specifications1018.3 Package Handling Guidelines1028.4 Package Insertion Specifications1028.5 Processor Mass Specification1028.6 Processor Materials1028.7 Processor Markings1038.8 Processor Land Coordinates1038.9 Processor Storage Specifications1049.0 Processor Ball and Signal Information106サイズ： 2.02MBページ数： 116Language: Englishマニュアルを開く
