Intel E3-1226 v3 マニュアル

目次

• Contents

  3
• Revision History

  8
• 1.0 Introduction

  9
  • 1.1 Supported Technologies

    10
  • 1.2 Interfaces

    11
  • 1.3 Power Management Support

    11
  • 1.4 Thermal Management Support

    12
  • 1.5 Package Support

    12
  • 1.6 Terminology

    12
  • 1.7 Related Documents

    15
• 2.0 Interfaces

  17
  • 2.1 System Memory Interface

    17
    • 2.1.1 System Memory Technology Supported

      18
    • 2.1.2 System Memory Timing Support

      19
    • 2.1.3 System Memory Organization Modes

      19
      • 2.1.3.1 System Memory Frequency

        21
      • 2.1.3.2 Intel® Fast Memory Access (Intel® FMA) Technology Enhancements

        21
      • 2.1.3.3 Data Scrambling

        21
  • 2.2 PCI Express* Interface

    22
    • 2.2.1 PCI Express* Support

      22
    • 2.2.2 PCI Express* Architecture

      23
    • 2.2.3 PCI Express* Configuration Mechanism

      23
  • 2.3 Direct Media Interface (DMI)

    25
  • 2.4 Processor Graphics

    27
  • 2.5 Processor Graphics Controller (GT)

    27
    • 2.5.1 3D and Video Engines for Graphics Processing

      28
    • 2.5.2 Multi Graphics Controllers Multi-Monitor Support

      30
  • 2.6 Digital Display Interface (DDI)

    30
  • 2.7 Intel® Flexible Display Interface (Intel® FDI)

    36
  • 2.8 Platform Environmental Control Interface (PECI)

    36
    • 2.8.1 PECI Bus Architecture

      36
• 3.0 Technologies

  38
  • 3.1 Intel® Virtualization Technology (Intel® VT)

    38
  • 3.2 Intel® Trusted Execution Technology (Intel® TXT)

    42
  • 3.3 Intel® Hyper-Threading Technology (Intel® HT Technology)

    43
  • 3.4 Intel® Turbo Boost Technology

    44
  • 3.5 Intel® Advanced Vector Extensions 2.0 (Intel® AVX2)

    44
  • 3.6 Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI)

    45
  • 3.7 Intel® Transactional Synchronization Extensions (Intel® TSX)

    45
  • 3.8 Intel® 64 Architecture x2APIC

    46
  • 3.9 Power Aware Interrupt Routing (PAIR)

    47
  • 3.10 Execute Disable Bit

    47
  • 3.11 Supervisor Mode Execution Protection (SMEP)

    47
• 4.0 Power Management

  48
  • 4.1 Advanced Configuration and Power Interface (ACPI) States Supported

    49
  • 4.2 Processor Core Power Management

    50
    • 4.2.1 Enhanced Intel® SpeedStep® Technology Key Features

      50
    • 4.2.2 Low-Power Idle States

      51
    • 4.2.3 Requesting Low-Power Idle States

      52
    • 4.2.4 Core C-State Rules

      53
    • 4.2.5 Package C-States

      54
  • 4.3 Integrated Memory Controller (IMC) Power Management

    58
    • 4.3.1 Disabling Unused System Memory Outputs

      58
    • 4.3.2 DRAM Power Management and Initialization

      58
      • 4.3.2.1 Initialization Role of CKE

        59
      • 4.3.2.2 Conditional Self-Refresh

        60
      • 4.3.2.3 Dynamic Power-Down

        60
      • 4.3.2.4 DRAM I/O Power Management

        60
    • 4.3.3 DRAM Running Average Power Limitation (RAPL)

      60
    • 4.3.4 DDR Electrical Power Gating (EPG)

      61
  • 4.4 PCI Express* Power Management

    61
  • 4.5 Direct Media Interface (DMI) Power Management

    61
  • 4.6 Graphics Power Management

    61
    • 4.6.1 Intel® Rapid Memory Power Management (Intel® RMPM)

      61
    • 4.6.2 Graphics Render C-State

      61
    • 4.6.3 Intel® Graphics Dynamic Frequency

      61
• 5.0 Thermal Management

  63
  • 5.1 Thermal Metrology

    64
  • 5.2 Fan Speed Control Scheme with Digital Thermal Sensor (DTS) 1.1

    64
  • 5.3 Fan Speed Control Scheme with Digital Thermal Sensor (DTS) 2.0

    66
  • 5.4 Intel® Xeon® Processor E3-1200 v3 Product Family Thermal Specifications

    67
  • 5.5 Processor Temperature

    69
  • 5.6 Adaptive Thermal Monitor

    69
  • 5.7 THERMTRIP# Signal

    72
  • 5.8 Digital Thermal Sensor

    73
    • 5.8.1 Digital Thermal Sensor Accuracy (Taccuracy)

      73
  • 5.9 Intel® Turbo Boost Technology Thermal Considerations

    74
    • 5.9.1 Intel® Turbo Boost Technology Power Control and Reporting

      74
    • 5.9.2 Package Power Control

      75
    • 5.9.3 Turbo Time Parameter

      75
• 6.0 Signal Description

  77
  • 6.1 System Memory Interface Signals

    77
  • 6.2 Memory Reference and Compensation

    79
  • 6.3 Reset and Miscellaneous Signals

    80
  • 6.4 PCI Express*-Based Interface Signals

    81
  • 6.5 Display Interface Signals

    81
  • 6.6 Direct Media Interface (DMI)

    82
  • 6.7 Phase Locked Loop (PLL) Signals

    82
  • 6.8 Testability Signals

    82
  • 6.9 Error and Thermal Protection Signals

    83
  • 6.10 Power Sequencing

    84
  • 6.11 Processor Power Signals

    84
  • 6.12 Sense Pins

    84
  • 6.13 Ground and Non-Critical to Function (NCTF) Signals

    85
  • 6.14 Processor Internal Pull-Up / Pull-Down Terminations

    85
• 7.0 Electrical Specifications

  86
  • 7.1 Integrated Voltage Regulator

    86
  • 7.2 Power and Ground Lands

    86
  • 7.3 VCC Voltage Identification (VID)

    86
  • 7.4 Reserved or Unused Signals

    91
  • 7.5 Signal Groups

    91
  • 7.6 Test Access Port (TAP) Connection

    93
  • 7.7 DC Specifications

    93
  • 7.8 Voltage and Current Specifications

    94
    • 7.8.1 PECI DC Characteristics

      99
    • 7.8.2 Input Device Hysteresis

      100
• 8.0 Package Mechanical Specifications

  101
  • 8.1 Processor Component Keep-Out Zone

    101
  • 8.2 Package Loading Specifications

    101
  • 8.3 Package Handling Guidelines

    102
  • 8.4 Package Insertion Specifications

    102
  • 8.5 Processor Mass Specification

    102
  • 8.6 Processor Materials

    102
  • 8.7 Processor Markings

    103
  • 8.8 Processor Land Coordinates

    103
  • 8.9 Processor Storage Specifications

    104
• 9.0 Processor Ball and Signal Information

  106