データシート (AT80573QJ0806M)目次Dual-Core Intel® Xeon® Processor 5200 Series11 Introduction91.1 Terminology101.2 State of Data131.3 References132 Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications152.1 Front Side Bus and GTLREF152.2 Power and Ground Lands152.3 Decoupling Guidelines162.3.1 VCC Decoupling162.3.2 VTT Decoupling162.3.3 Front Side Bus AGTL+ Decoupling162.4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking172.4.1 Front Side Bus Frequency Select Signals (BSEL[2:0])172.4.2 PLL Power Supply182.5 Voltage Identification (VID)182.6 Reserved, Unused, and Test Signals212.7 Front Side Bus Signal Groups222.8 CMOS Asynchronous and Open Drain Asynchronous Signals242.9 Test Access Port (TAP) Connection242.10 Platform Environmental Control Interface (PECI) DC Specifications242.10.1 DC Characteristics242.10.2 Input Device Hysteresis252.11 Mixing Processors262.12 Absolute Maximum and Minimum Ratings262.13 Processor DC Specifications272.13.1 Flexible Motherboard Guidelines (FMB)272.13.2 VCC Overshoot Specification352.13.3 Die Voltage Validation352.14 AGTL+ FSB Specifications363 Mechanical Specifications393.1 Package Mechanical Drawings393.2 Processor Component Keepout Zones433.3 Package Loading Specifications433.4 Package Handling Guidelines443.5 Package Insertion Specifications443.6 Processor Mass Specifications443.7 Processor Materials443.8 Processor Markings443.9 Processor Land Coordinates454 Land Listing474.1 Dual-Core Intel® Xeon® Processor 5200 Series Pin Assignments474.1.1 Land Listing by Land Name474.1.2 Land Listing by Land Number575 Signal Definitions675.1 Signal Definitions676 Thermal Specifications756.1 Package Thermal Specifications756.1.1 Thermal Specifications756.1.2 Thermal Metrology846.2 Processor Thermal Features856.2.1 Intel® Thermal Monitor Features856.2.2 On-Demand Mode876.2.3 PROCHOT# Signal886.2.4 FORCEPR# Signal886.2.5 THERMTRIP# Signal886.3 Platform Environment Control Interface (PECI)896.3.1 Introduction896.3.2 PECI Specifications907 Features937.1 Power-On Configuration Options937.2 Clock Control and Low Power States937.2.1 Normal State947.2.2 HALT or Extended HALT State947.2.3 Stop-Grant State967.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State967.3 Enhanced Intel SpeedStep® Technology978 Boxed Processor Specifications998.1 Introduction998.2 Mechanical Specifications1018.2.1 Boxed Processor Heat Sink Dimensions (CEK)1018.2.2 Boxed Processor Heat Sink Weight1098.2.3 Boxed Processor Retention Mechanism and Heat Sink Support (CEK)1098.3 Electrical Requirements1098.3.1 Fan Power Supply (Active CEK)1098.3.2 Boxed Processor Cooling Requirements1108.4 Boxed Processor Contents1119 Debug Tools Specifications1139.1 Debug Port System Requirements1139.2 Target System Implementation1139.2.1 System Implementation1139.3 Logic Analyzer Interface (LAI)1139.3.1 Mechanical Considerations1149.3.2 Electrical Considerations114サイズ： 2.52MBページ数： 114Language: Englishマニュアルを開く
データシート (EU80573KJ0806M)目次Dual-Core Intel® Xeon® Processor 5200 Series11 Introduction91.1 Terminology101.2 State of Data131.3 References132 Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications152.1 Front Side Bus and GTLREF152.2 Power and Ground Lands152.3 Decoupling Guidelines162.3.1 VCC Decoupling162.3.2 VTT Decoupling162.3.3 Front Side Bus AGTL+ Decoupling162.4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking172.4.1 Front Side Bus Frequency Select Signals (BSEL[2:0])172.4.2 PLL Power Supply182.5 Voltage Identification (VID)182.6 Reserved, Unused, and Test Signals212.7 Front Side Bus Signal Groups222.8 CMOS Asynchronous and Open Drain Asynchronous Signals242.9 Test Access Port (TAP) Connection242.10 Platform Environmental Control Interface (PECI) DC Specifications242.10.1 DC Characteristics242.10.2 Input Device Hysteresis252.11 Mixing Processors262.12 Absolute Maximum and Minimum Ratings262.13 Processor DC Specifications272.13.1 Flexible Motherboard Guidelines (FMB)272.13.2 VCC Overshoot Specification352.13.3 Die Voltage Validation352.14 AGTL+ FSB Specifications363 Mechanical Specifications393.1 Package Mechanical Drawings393.2 Processor Component Keepout Zones433.3 Package Loading Specifications433.4 Package Handling Guidelines443.5 Package Insertion Specifications443.6 Processor Mass Specifications443.7 Processor Materials443.8 Processor Markings443.9 Processor Land Coordinates454 Land Listing474.1 Dual-Core Intel® Xeon® Processor 5200 Series Pin Assignments474.1.1 Land Listing by Land Name474.1.2 Land Listing by Land Number575 Signal Definitions675.1 Signal Definitions676 Thermal Specifications756.1 Package Thermal Specifications756.1.1 Thermal Specifications756.1.2 Thermal Metrology846.2 Processor Thermal Features856.2.1 Intel® Thermal Monitor Features856.2.2 On-Demand Mode876.2.3 PROCHOT# Signal886.2.4 FORCEPR# Signal886.2.5 THERMTRIP# Signal886.3 Platform Environment Control Interface (PECI)896.3.1 Introduction896.3.2 PECI Specifications907 Features937.1 Power-On Configuration Options937.2 Clock Control and Low Power States937.2.1 Normal State947.2.2 HALT or Extended HALT State947.2.3 Stop-Grant State967.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State967.3 Enhanced Intel SpeedStep® Technology978 Boxed Processor Specifications998.1 Introduction998.2 Mechanical Specifications1018.2.1 Boxed Processor Heat Sink Dimensions (CEK)1018.2.2 Boxed Processor Heat Sink Weight1098.2.3 Boxed Processor Retention Mechanism and Heat Sink Support (CEK)1098.3 Electrical Requirements1098.3.1 Fan Power Supply (Active CEK)1098.3.2 Boxed Processor Cooling Requirements1108.4 Boxed Processor Contents1119 Debug Tools Specifications1139.1 Debug Port System Requirements1139.2 Target System Implementation1139.2.1 System Implementation1139.3 Logic Analyzer Interface (LAI)1139.3.1 Mechanical Considerations1149.3.2 Electrical Considerations114サイズ： 2.52MBページ数： 114Language: Englishマニュアルを開く
