Intel i5-2450M マニュアル

目次

• Contents

  3
  • Figures

    6
  • Tables

    7
• Revision History

  9
• 1.0 Introduction

  10
  • 1.1 Supported Technologies

    11
  • 1.2 Power Management Support

    12
  • 1.3 Thermal Management Support

    12
  • 1.4 Package Support

    13
  • 1.5 Processor Testability

    13
  • 1.6 Terminology

    13
  • 1.7 Related Documents

    16
• 2.0 Interfaces

  18
  • 2.1 System Memory Interface

    18
    • 2.1.1  System Memory Technology Supported

      18
    • 2.1.2 System Memory Timing Support

      19
    • 2.1.3  Intel® Fast Memory Access (Intel® FMA)

      20
    • 2.1.4 System Memory Frequency

      21
    • 2.1.5  System Memory Organization Modes

      21
    • 2.1.6  Data Scrambling

      22
  • 2.2 Processor Graphics

    22
  • 2.3 Processor Graphics Controller (GT)

    23
    • 2.3.1 3D and Video Engines for Graphics Processing

      23
  • 2.4 Digital Display Interface (DDI)

    25
  • 2.5 Platform Environmental Control Interface (PECI)

    31
    • 2.5.1 PECI Bus Architecture

      31
• 3.0 Technologies

  33
  • 3.1 Intel® Virtualization Technology (Intel® VT)

    33
  • 3.2 Intel® Trusted Execution Technology (Intel® TXT)

    37
  • 3.3 Intel® Hyper-Threading Technology (Intel® HT Technology)

    38
  • 3.4 Intel® Turbo Boost Technology 2.0

    39
  • 3.5 Intel® Advanced Vector Extensions 2.0 (Intel® AVX2)

    39
  • 3.6 Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI)

    39
  • 3.7 Intel® 64 Architecture x2APIC

    40
  • 3.8  Power Aware Interrupt Routing (PAIR)

    42
  • 3.9 Execute Disable Bit

    42
  • 3.10 Intel® Device Protection with Boot Guard

    42
  • 3.11  Supervisor Mode Execution Protection (SMEP)

    42
  • 3.12  Supervisor Mode Access Protection (SMAP)

    43
  • 3.13  Intel® Transactional Synchronization Extensions - New Instructions (Intel® TSX-NI)

    43
• 4.0 Power Management

  44
  • 4.1 Advanced Configuration and Power Interface (ACPI) States Supported

    45
  • 4.2 Processor Core Power Management

    46
    • 4.2.1 Enhanced Intel® SpeedStep® Technology Key Features

      46
    • 4.2.2 Low-Power Idle States

      47
    • 4.2.3 Requesting Low-Power Idle States

      48
    • 4.2.4 Core C-State Rules

      48
    • 4.2.5 Package C-States

      50
    • 4.2.6 Package C-States and Display Resolutions

      53
  • 4.3 Integrated Memory Controller (IMC) Power Management

    54
    • 4.3.1 Disabling Unused System Memory Outputs

      55
    • 4.3.2 DRAM Power Management and Initialization

      55
      • 4.3.2.1 Initialization Role of CKE

        56
      • 4.3.2.2 Conditional Self-Refresh

        56
      • 4.3.2.3 Dynamic Power-Down

        57
      • 4.3.2.4 DRAM I/O Power Management

        57
    • 4.3.3 DDR Electrical Power Gating (EPG)

      57
  • 4.4 Graphics Power Management

    58
    • 4.4.1 Intel® Rapid Memory Power Management (Intel® RMPM)

      58
    • 4.4.2 Graphics Render C-State

      58
    • 4.4.3 Intel® Smart 2D Display Technology (Intel® S2DDT)

      58
    • 4.4.4 Intel® Graphics Dynamic Frequency

      58
    • 4.4.5  Intel® Display Power Saving Technology (Intel® DPST)

      59
    • 4.4.6 Intel® Automatic Display Brightness

      59
    • 4.4.7 Intel® Seamless Display Refresh Rate Technology (Intel® SDRRS Technology)

      59
• 5.0 Thermal Management

  60
  • 5.1 Thermal Considerations

    60
  • 5.2 Intel® Turbo Boost Technology 2.0 Power Monitoring

    61
  • 5.3 Intel® Turbo Boost Technology 2.0 Power Control

    61
    • 5.3.1 Package Power Control

      61
    • 5.3.2 Turbo Time Parameter

      62
  • 5.4 Configurable TDP (cTDP) and Low-Power Mode

    62
    • 5.4.1 Configurable TDP

      63
    • 5.4.2 Low-Power Mode

      63
  • 5.5 Thermal and Power Specifications

    64
  • 5.6 Thermal Management Features

    66
    • 5.6.1 Adaptive Thermal Monitor

      66
      • 5.6.1.1 Thermal Control Circuit (TCC) Activation Offset

        67
      • 5.6.1.2 Frequency / Voltage Control

        67
      • 5.6.1.3 Clock Modulation

        67
    • 5.6.2 Digital Thermal Sensor

      68
      • 5.6.2.1 Digital Thermal Sensor Accuracy (Taccuracy)

        69
      • 5.6.2.2  Fan Speed Control with Digital Thermal Sensor

        69
    • 5.6.3 PROCHOT# Signal

      69
      • 5.6.3.1 Bi-Directional PROCHOT#

        69
      • 5.6.3.2 Voltage Regulator Protection using PROCHOT#

        69
      • 5.6.3.3 Thermal Solution Design and PROCHOT# Behavior

        70
      • 5.6.3.4 Low-Power States and PROCHOT# Behavior

        70
      • 5.6.3.5 THERMTRIP# Signal

        70
      • 5.6.3.6 Critical Temperature Detection

        70
    • 5.6.4 On-Demand Mode

      70
      • 5.6.4.1 MSR Based On-Demand Mode

        71
      • 5.6.4.2 I/O Emulation-Based On-Demand Mode

        71
    • 5.6.5 Intel® Memory Thermal Management

      71
• 6.0 Signal Description

  72
  • 6.1 System Memory Interface Signals

    72
  • 6.2 Memory Compensation and Miscellaneous Signals

    74
  • 6.3 Reset and Miscellaneous Signals

    74
  • 6.4 embedded DisplayPort* (eDP*) Signals

    75
  • 6.5 Display Interface Signals

    75
  • 6.6 Testability Signals

    75
  • 6.7 Error and Thermal Protection Signals

    76
  • 6.8 Power Sequencing Signals

    77
  • 6.9 Processor Power Signals

    77
  • 6.10 Sense Signals

    78
  • 6.11 Ground and Non-Critical to Function (NCTF) Signals

    78
  • 6.12 Processor Internal Pull-Up / Pull-Down Terminations

    79
• 7.0 Electrical Specifications

  80
  • 7.1 Integrated Voltage Regulator

    80
  • 7.2 Power and Ground Pins

    80
  • 7.3 VCC Voltage Identification (VID)

    80
  • 7.4 Reserved or Unused Signals

    85
  • 7.5 Signal Groups

    85
  • 7.6 Test Access Port (TAP) Connection

    87
  • 7.7  DC Specifications

    87
  • 7.8 Voltage and Current Specifications

    87
    • 7.8.1 Platform Environment Control Interface (PECI) DC Characteristics

      94
    • 7.8.2 Input Device Hysteresis

      95
• 8.0 Package Specifications

  96
  • 8.1 Package Mechanical Attributes

    96
  • 8.2 Package Loading Specifications

    97
  • 8.3 Package Storage Specifications

    97
• 9.0 Processor Ball and Signal Information

  98
  • 9.1 Intel® Core™ M Processor Family Ball Information (BGA1234)

    98
  • 9.2 U-Processor Ball Information (BGA1168)

    111