データシート (CL8064701477000)目次Contents3Figures6Tables7Revision History91.0 Introduction101.1 Supported Technologies111.2 Power Management Support121.3 Thermal Management Support121.4 Package Support131.5 Processor Testability131.6 Terminology131.7 Related Documents162.0 Interfaces172.1 System Memory Interface172.1.1 System Memory Technology Supported172.1.2 System Memory Timing Support192.1.3 System Memory Organization Modes192.1.4 System Memory Frequency202.1.5 Intel® Fast Memory Access (Intel® FMA) Technology Enhancements202.1.6 Data Scrambling212.1.7 DRAM Clock Generation212.1.8 DRAM Reference Voltage Generation212.2 Processor Graphics222.3 Processor Graphics Controller (GT)222.3.1 3D and Video Engines for Graphics Processing222.4 Digital Display Interface (DDI)242.5 Platform Environmental Control Interface (PECI)292.5.1 PECI Bus Architecture293.0 Technologies313.1 Intel® Virtualization Technology (Intel® VT)313.2 Intel® Trusted Execution Technology (Intel® TXT)353.3 Intel® Hyper-Threading Technology (Intel® HT Technology)363.4 Intel® Turbo Boost Technology 2.0373.5 Intel® Advanced Vector Extensions 2.0 (Intel® AVX2)373.6 Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI)383.7 Intel® 64 Architecture x2APIC383.8 Power Aware Interrupt Routing (PAIR)403.9 Execute Disable Bit403.10 Intel® Boot Guard403.11 Supervisor Mode Execution Protection (SMEP)403.12 Intel® Transactional Synchronization Extensions - New Instructions (Intel® TSX-NI)414.0 Power Management424.1 Advanced Configuration and Power Interface (ACPI) States Supported434.2 Processor Core Power Management444.2.1 Enhanced Intel® SpeedStep® Technology Key Features444.2.2 Low-Power Idle States454.2.3 Requesting Low-Power Idle States464.2.4 Core C-State Rules464.2.5 Package C-States484.2.6 Package C-States and Display Resolutions514.3 Integrated Memory Controller (IMC) Power Management534.3.1 Disabling Unused System Memory Outputs534.3.2 DRAM Power Management and Initialization534.3.2.1 Initialization Role of CKE554.3.2.2 Conditional Self-Refresh554.3.2.3 Dynamic Power-Down554.3.2.4 DRAM I/O Power Management564.3.3 DDR Electrical Power Gating (EPG)564.4 Graphics Power Management564.4.1 Intel® Rapid Memory Power Management (Intel® RMPM)564.4.2 Graphics Render C-State564.4.3 Intel® Smart 2D Display Technology (Intel® S2DDT)574.4.4 Intel® Graphics Dynamic Frequency574.4.5 Intel® Display Power Saving Technology (Intel® DPST)574.4.6 Intel® Automatic Display Brightness584.4.7 Intel® Seamless Display Refresh Rate Technology (Intel® SDRRS Technology)585.0 Thermal Management595.1 Thermal Considerations595.2 Intel® Turbo Boost Technology 2.0 Power Monitoring605.3 Intel® Turbo Boost Technology 2.0 Power Control605.3.1 Package Power Control605.3.2 Turbo Time Parameter615.4 Configurable TDP (cTDP) and Low-Power Mode615.4.1 Configurable TDP615.4.2 Low-Power Mode625.5 Thermal and Power Specifications625.6 Thermal Management Features655.6.1 Adaptive Thermal Monitor655.6.1.1 Thermal Control Circuit (TCC) Activation Offset665.6.1.2 Frequency / Voltage Control665.6.1.3 Clock Modulation675.6.2 Digital Thermal Sensor675.6.2.1 Digital Thermal Sensor Accuracy (Taccuracy)685.6.2.2 Fan Speed Control with Digital Thermal Sensor685.6.3 PROCHOT# Signal685.6.3.1 Bi-Directional PROCHOT#685.6.3.2 Voltage Regulator Protection using PROCHOT#695.6.3.3 Thermal Solution Design and PROCHOT# Behavior695.6.3.4 Low-Power States and PROCHOT# Behavior695.6.3.5 THERMTRIP# Signal695.6.3.6 Critical Temperature Detection695.6.4 On-Demand Mode705.6.4.1 MSR Based On-Demand Mode705.6.4.2 I/O Emulation-Based On-Demand Mode705.6.5 Intel® Memory Thermal Management705.6.6 Scenario Design Power (SDP)716.0 Signal Description726.1 System Memory Interface Signals726.2 Memory Compensation and Miscellaneous Signals756.3 Reset and Miscellaneous Signals766.4 embedded DisplayPort* (eDP*) Signals776.5 Display Interface Signals776.6 Testability Signals776.7 Error and Thermal Protection Signals786.8 Power Sequencing Signals796.9 Processor Power Signals796.10 Sense Signals806.11 Ground and Non-Critical to Function (NCTF) Signals806.12 Processor Internal Pull-Up / Pull-Down Terminations807.0 Electrical Specifications827.1 Integrated Voltage Regulator827.2 Power and Ground Pins827.3 VCC Voltage Identification (VID)827.4 Reserved or Unused Signals877.5 Signal Groups877.6 Test Access Port (TAP) Connection897.7 DC Specifications897.8 Voltage and Current Specifications907.8.1 Platform Environment Control Interface (PECI) DC Characteristics967.8.2 Input Device Hysteresis978.0 Package Specifications988.1 Package Mechanical Attributes988.2 Package Loading Specifications988.3 Package Storage Specifications999.0 Processor Ball and Signal Information100サイズ: 2.16MBページ数: 123Language: Englishマニュアルを開く